LAN83C185 datasheet(41/61 Pages) SMSC

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High Performance Single Chip Low Power 10/100 Ethernet Physical Layer Transceiver (PHY)

Datasheet

SMSC LAN83C185

Rev. 0.8 (11-16-04)

DATASHEET

Table 5.47 Register 23 - TSTWRITE

ADDRESS

NAME

DESCRIPTION

MODE

DEFAULT

23.15:0

WRITE_DATA

This field contains the data that will be written to a

specific register on the “Programming” transaction.

Table 5.48 Register 27 - Special Control/Status Indications

ADDRESS

NAME

DESCRIPTION

MODE

DEFAULT

27.15:13

Reserved

27.12

SWRST_FAST

1 = Accelerates SW reset counter from 256 ms to 10

us for production testing.

27:11

SQEOFF

Disable the SQE test (Heartbeat):

0 - SQE test is enabled.

1 - SQE test is disabled.

RW,

NASR

27:10

VCOOFF_LP

Forces the Receive PLL 10M to lock on the reference

clock at all times:

0 - Receive PLL 10M can lock on reference or line as

needed (normal operation)

1 - Receive PLL 10M is locked on the reference clock.

In this mode 10M data packets cannot be received.

RW,

NASR

27.9

Reserved

Write as 0. Ignore on read.

27.8

Reserved

Write as 0. Ignore on read.

27.7

Reserved

Write as 0. Ignore on read

27.6

Reserved

Write as 0. Ignore on read.

27.5

Reserved

Write as 0. Ignore on read.

27.4

XPOL

Polarity state of the 10Base-T:

0 - Normal polarity

1 - Reversed polarity

27.3:0

AUTONEGS

Auto-negotiation “ARB” State-machine state

1011

Table 5.49 Register 28 - Special Internal Testability Controls

ADDRESS

NAME

DESCRIPTION

MODE

DEFAULT

28.15:0

Reserved

Do not write to this register. Ignore on read.

N/A

Table 5.50 Register 29 - Interrupt Source Flags

ADDRESS

NAME

DESCRIPTION

MODE

DEFAULT

29.15:8

Reserved

Ignore on read.

RO/

29.7

INT7

1 = ENERGYON generated

0 = not source of interrupt

RO/

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