MAX5590 datasheet(16/33 Pages) MAXIM

16 / 33 page

Buffered, Fast-Settling, Octal, 12/10/8-Bit,

Voltage-Output DACs

______________________________________________________________________________________

Detailed Description

The MAX5590–MAX5595 octal, 12/10/8-bit, voltage-out-

put DACs offer buffered outputs and a 3µs maximum

settling time at the 12-bit level. The DACs operate from a

single 2.7V to 5.25V analog supply and a separate 1.8V

to AVDD digital supply. The MAX5590–MAX5595 include

an input register and DAC register for each channel and

a 16-bit data-in/data-out shift register. The 3-wire serial

interface is compatible with SPI, QSPI, MICROWIRE, and

DSP applications. The MAX5590– MAX5595 provide two

user-programmable digital I/O ports, which are pro-

grammed through the serial interface. The externally

selectable power-up states of the DAC outputs are either

zero scale, midscale, or full scale.

Reference Input

The reference input, REF, accepts both AC and DC val-

ues with a voltage range extending from analog ground

(AGND) to AVDD. The voltage at REF sets the full-scale

output of the DACs. Determine the output voltage using

the following equations:

Unity-gain versions:

VOUT_ = (VREF x CODE) / 2N

Force-sense versions (FB_ connected to OUT_):

VOUT = 0.5 x (VREF x CODE) / 2N

where CODE is the numeric value of the DAC’s binary

input code and N is the bits of resolution. For the

MAX5590/MAX5591, N = 12 and CODE ranges from 0

to 4095. For the MAX5592/MAX5593, N = 10 and

CODE ranges from 0 to 1023. For the MAX5594/

MAX5595, N = 8 and CODE ranges from 0 to 255.

Output Buffers

The DACA and DACH output-buffer amplifiers of the

MAX5590–MAX5595 are unity-gain stable with Rail-to-

Rail® output voltage swings and a typical slew rate

of 3.6V/µs (FAST mode). The MAX5590/MAX5592/

MAX5594 provide unity-gain outputs, while the

MAX5591/MAX5593/MAX5595 provide force-sense out-

puts. For the MAX5591/MAX5593/MAX5595, access to

the output amplifier’s inverting input provides flexibility

in output gain setting and signal conditioning (see the

Applications Information section).

The MAX5590–MAX5595 offer FAST and SLOW settling-

time modes. In the SLOW mode, the settling time is 6µs

(max), and the supply current is 3.2mA (max). In the

FAST mode, the settling time is 3µs (max), and the sup-

ply current is 8mA (max). See the Digital Interface section

for settling-time mode programming details.

Use the serial interface to set the shutdown output

impedance of the amplifiers to 1k

Ω or 100kΩ for the

MAX5590/MAX5592/MAX5594 and 1k

Ω or high imped-

ance for the MAX5591/MAX5593/MAX5595. The DAC

outputs can drive a 10k

Ω (typ) load and are stable with

up to 500pF (typ) of capacitive load.

Power-On Reset

At power-up, all DAC outputs power up to full scale,

midscale, or zero scale, depending on the configuration

of the PU input. Connect PU to DVDD to set OUT_ to full

scale upon power-up. Connect PU to digital ground

(DGND) at power-up to set OUT_ to zero scale. Leave

PU floating to set OUT_ to midscale.

Digital Interface

The MAX5590–MAX5595 use a 3-wire serial interface

that is compatible with SPI, QSPI, MICROWIRE, and DSP

protocol applications (Figures 1 and 2). Connect DSP to

DVDD before power-up to clock data in on the rising

edge of SCLK. Connect DSP to DGND before power-up

to clock data in on the falling edge of SCLK. After power-

up, the device enters DSP frame-sync mode on the first

rising edge of DSP. Refer to the MAX5590–MAX5595

Programmer’s Handbook for details.

The MAX5590–MAX5595 include a 16-bit input shift

through the serial interface. The 16 bits can be sent in

two serial 8-bit packets or one 16-bit word (CS must

remain low until all 16 bits are transferred). The data is

loaded MSB first. For the MAX5590/MAX5591, the 16

bits consist of 4 control bits (C3–C0) and 12 data bits

(D11–D0) (see Table 1). For the 10-bit MAX5592/

MAX5593 devices, D11–D2 are the data bits and D1

and D0 are sub-bits. For the 8-bit MAX5594/

MAX5595 devices, D11–D4 are the data bits and

D3–D0 are sub-bits. Set all sub-bits to zero for optimum

performance.

Each DAC channel includes two registers: an input reg-

ister and the DAC register. At power-up, the DAC out-

put is set according to the state of PU. The DACs are

double-buffered, which allows any of the following for

each channel:

• Loading the input register without updating the DAC

• Updating the DAC register from the input register

• Updating the input and DAC registers simultaneously

Rail-to-Rail is a registered trademark of Nippon Motorola, Ltd.

MAX5590 Datasheet(PDF) 16 Page - Maxim Integrated Products

MAX5590 Datasheet(HTML) 16 Page - Maxim Integrated Products

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33

Datasheet Download

Link URL