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MAX5590 Datasheet(PDF) 25 Page - Maxim Integrated Products |
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MAX5590 Datasheet(HTML) 25 Page - Maxim Integrated Products |
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25 / 33 page ![]() Buffered, Fast-Settling, Octal, 12/10/8-Bit, Voltage-Output DACs ______________________________________________________________________________________ 25 Settling-Time-Mode Write Example: To configure DACA and DACD into FAST mode and DACB and DACC into SLOW mode, use the command in Table 13. To read back the settling-time-mode bits, use the com- mand in Table 14. CPOL and CPHA Control Bits The CPOL and CPHA control bits of the MAX5590–MAX5595 are defined the same as the CPOL and CPHA bits in the SPI standard. Set the DAC’s CPOL and CPHA bits to CPOL = 0 and CPHA = 0 or CPOL = 1 and CPHA = 1 for MICROWIRE and SPI applications requiring the clocking of data in on the ris- ing edge of SCLK. Set the DAC’s CPOL and CPHA bits to CPOL = 0 and CPHA = 1 or CPOL = 1 and CPHA = 0 for DSP and SPI applications, requiring the clocking of data in on the falling edge of SCLK (refer to the Programmer’s Handbook and see Table 15 for details). At power-up, if DSP = DVDD, the default value of CPHA is zero and if DSP = DGND, the default value of CPHA is one. The default value of CPOL is zero at power-up. To write to the CPOL and CPHA bits, use the command in Table 16. To read back the device’s CPOL and CPHA bits, use the command in Table 17. Table 13. Settling-Time-Mode Write Example DATA CONTROL BITS DATA BITS DIN 10 11 10 0 0 X X X X 10 01 X = Don’t care. Table 14. Settling-Time-Mode Read Command DATA CONTROL BITS DATA BITS DIN 1 0 1 110 01 X X XX XXX X DOUTRB XX X XXX XX SPDH SPDGSPDFSPDE SPDD SPDC SPDB SPDA Table 17. CPOL and CPHA Read Command DATA CONTROL BITS DATA BITS DIN 1 1 0 0 0 0 0 1 X X X X X X X X DOUTRB XX X X X X X X XX X X X X CPOL CPHA Table 15. CPOL and CPHA Bits CPOL CPHA DESCRIPTION 00 Default values at power-up when DSP is connected to DVDD. Data is clocked in on the rising edge of SCLK. 01 Default values at power-up when DSP is connected to DGND. Data is clocked in on the falling edge of SCLK. 10 Data is clocked in on the falling edge of SCLK. 11 Data is clocked in on the rising edge of SCLK. Table 16. CPOL and CPHA Write Command DATA CONTROL BITS DATA BITS DIN 11 0 0 00 00X X X X X X CPOL CPHA X = Don’t care. X = Don’t care. X = Don’t care. |
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