Buffered, Fast-Settling, Octal, 12/10/8-Bit,

Voltage-Output DACs

______________________________________________________________________________________

17

Table 1. Serial Write Data Format

MSB

16 BITS OF SERIAL DATA

LSB

CONTROL BITS

DATA BITS

C3

C2

C1

C0

D11

D10

D9

D8

D7

D6

D5

D4

D3

D2

D1

D0

Figure 1. Serial-Interface Timing Diagram (DSP Mode Disabled)

Figure 2. Serial-Interface Timing Diagram (DSP Mode Enabled)

SCLK

DIN

CS

DOUTDC1*

DOUTDC0

OR

DOUTRB*

*UPIO1/UPIO2 CONFIGURED AS DOUTDC_ (DAISY-CHAIN DATA OUTPUT, MODE 0 OR 1) OR DOUTRB (READ-BACK DATA OUTPUT).

SEE THE DATA OUTPUT (DOUTRB, DOUTDC0, DOUTDC1) SECTION FOR DETAILS.

DOUT VALID

DOUT VALID

C1

D0

C2

C3

SCLK

DIN

CS

DSP

DOUTDC0*

DOUTDC1

OR

DOUTRB*

*UPIO1/UPIO2 CONFIGURED AS DOUTDC_ (DAISY-CHAIN DATA OUTPUT, MODE 0 OR 1) OR DOUTRB (READ-BACK DATA OUTPUT).

SEE THE DATA OUTPUT (DOUTRB, DOUTDC0, DOUTDC1) SECTION FOR DETAILS.

C3

C2

C1

D0

DOUT VALID

DOUT VALID