AD1871 datasheet(18/28 Pages) AD

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AD1871

–18–

REV. 0

2S Mode

In I

2S Mode, the data is left-justified, MSB first, with the MSB

placed in the second BCLK period following the transition of

the LRCLK. A high-to-low transition of the LRCLK signifies

the beginning of the left channel data transfer, while a low-to-

high transition on the LRCLK signifies the beginning of the

right channel data transfer (see Figure 12).

LEFT CHANNEL

RIGHT CHANNEL

MSB–2

MSB–1

LSB+2

LSB+1

LSB

MSB–2

MSB–1

MSB

LSB+2 LSB+1

LSB

MSB

LRCLK

BCLK

DOUT

MSB

Figure 12. I2S Mode

LJ Mode

In LJ Mode, the data is left-justified, MSB first, with the MSB

placed in the first BCLK period following the transition of the

LRCLK. A high-to-low transition of the LRCLK signifies the

beginning of the right channel data transfer, while a low-to-high

transition on the LRCLK signifies the beginning of the left

channel data transfer (see Figure 13).

MSB–2

MSB–1

LSB+2

LSB+1

LSB

MSB–2

MSB–1

MSB

LSB+2

LSB+1

LSB

MSB–1

MSB

LRCLK

BCLK

DOUT

LEFT CHANNEL

RIGHT CHANNEL

MSB

Figure 13. Left-Justified Mode

RJ Mode

In RJ Mode, the data is right-justified, LSB last, with the

LSB placed in the last BCLK period preceding the transition

of the LRCLK. A high-to-low transition of the LRCLK signifies

the beginning of the right channel data transfer, while a low-to-

high transition on the LRCLK signifies the beginning of the left

channel data transfer (see Figure 14).

DOUT

LSB

MSB–2

MSB–1

LSB+2 LSB+1

MSB–2

MSB–1

MSB

LSB+2 LSB+1

LSB

BCLK

LRCLK

LEFT CHANNEL

RIGHT CHANNEL

MSB

LSB

Figure 14. Right-Justified Mode

DSP Mode

In DSP Mode, the LRCLK signal becomes a frame sync signal

that pulses high for the BCLK period prior to the MSB (or in

the BCLK period of the previous LSB–32 bits). The data is left-

justified, MSB first, with the MSB placed in the BCLK period

following the LRCLK pulse (see Figure 15).

In I

2S and LJ Modes, since the data is left-justified, differences in

data word-width between the AD1871 and the controller are not

catastrophic since the MSBs are guaranteed to be transferred.

There may, however, be a slight reduction in performance

depending on the scale of the mismatch. In RJ Mode, however,

differences in word-width between the AD1871 and controller

have a catastrophic effect on signal performance as the MSBs

of each sample may be lost due to the mismatch.

DOUT

MSB–1

LSB+2

LSB+1

LSB

MSB–1

LSB+2

LSB+1

LSB

MSB

MSB–1

MSB

LRCLK

LEFT CHANNEL

RIGHT CHANNEL

BCLK

MSB

Figure 15. DSP Mode

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