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AD1871

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Peak Reading Registers

The Peak Reading Registers are read-only registers that can be

enabled to track-and-hold the peak ADC reading from each

channel. The peak reading feature is enabled by setting Bit PRE

in Control Register I. The peak reading value is contained in the

six LSBs of the 10-bit readback word. The result is binary coded

where each LSB is equivalent to –1 dBFS with all zeros cor-

responding to full scale (0 dBFS) and all ones corresponding

to –63 dBFS (see Table XVI). When Bit PRE is set, the peak

reading per channel is stored in the appropriate peak register.

Once the register is read, the register value is set to zero and is

updated by subsequent conversions.

Table XVI. Peak Reading Result Format

Code

AxP

Level

0 dBFS

–1 dBFS

–2 dBFS

110

–62 dBFS

111

–63 dBFS

A Peak Reading Register read cycle is detailed in Figure 21.

EXTERNAL CONTROL

The AD1871 can be configured for external hardware control of

a subset of the device functionality. This functionality includes

Master/Slave Mode select, MCLK select, and serial data

format select. External control is enabled by tying the XCTRL

Pin high as shown in Figure 22.

AD1871

XCTRL

VDD

Figure 22. External Control Configuration

Table XIV. Peak Reading Register I (Address 0011b, Read-Only)

15–12

432

0011

A0P5

A0P4

A0P3

A0P2

A0P1

A0P0

9–6

Reserved

(Always Set to Zero)

5–0

A0P5–A0P0

Left Channel Peak Reading (Valid Only When PRE = 1)

Table XV. Peak Reading Register II (Address 0100b, Read-Only)

15–12

432

0100

A1P5

A1P4

A1P3

A1P2

A1P1

A1P0

9–6

Reserved

(Always Set to Zero)

5–0

A1P5–A1P0

Right Channel Peak Reading (Valid Only When PRE = 1)

Master/Slave Select

The

Master/Slave hardware select (Pin 5, CLATCH/[M/S])

is equivalent to setting the

M/S Bit of Control Register II. If set

low, the device is placed in Master Mode, whereby the LRCLK

and BCLK signals are outputs from the AD1871.

When

M/S is set high, the device is in Slave Mode, whereby the

LRCK and BCLK signals are inputs to the AD1871.

MCLK Mode Select

The MCLK Mode hardware select (Pin 2, CCLK/[

256/512]) is

a subset of the MCLK Mode selection that is determined by

Bits CM1–CM0 of Control Register X. When the hardware pin

is low, the device operates with an MCLK that is 256

¥ fS; if the

pin is set high, the device operates with an MCLK that is 512

¥ fS.

Serial Data Format Select

The Serial Data Format hardware select (Pins 3 and 4, DF0/

COUT and DF1/CIN) is equivalent to setting Bits DF1–DF0 of

Control Register II. See Table VIII.

In External Control Mode, all functions other than those

selected by the hardware select pins (

Master/Slave Mode select,

MCLK select, and Serial Data Format select) are in their

default (power-on) state.

MODULATOR MODE

When the device is in Modulator Mode (MME Bit is set to 1),

the D[0–3] pins are enabled as data outputs, while the COUT

pin becomes MODCLK, a high speed sampling clock (nomi-

nally at 128

fS). The MODCLK enables successive data from

the left and right channel modulators with left channel modula-

tor data being valid in the low phase of MODCLK, while right

channel modulator data is valid under the high phase of MODCLK

(see Modulator Mode Timing in Figure 6).

The Modulator Mode is designed to be used for applications

such as direct stream digital (DSD) where modulator data is

stored directly to the recording media without decimation and

filtering to a lower sample rate. DSD is specified at a rate of

fS, whereas the AD1871 outputs at 128

fS,

requiring an intermediate remodulator that downsamples to

fS and generates a single-bit output steam.

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