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CAP1214 Datasheet(PDF) 67 Page - Microchip Technology |
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CAP1214 Datasheet(HTML) 67 Page - Microchip Technology |
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67 / 107 page ![]() Multiple Channel Capacitive Touch Sensor and LED Driver Datasheet SMSC CAP1214 67 Revision 1.0 (08-30-10) DATASHEET 6.30 Lid Closure Threshold Registers The Lid Closure Threshold Registers control the value of a secondary internal threshold to detect noise potentially generated by lid closure. If a Capacitive Touch Sensor output exceeds the Lid Closure Threshold, the appropriate status bit is set in the Lid Closure Status register (see Section 6.8). The Lid Closure Threshold is proportional to the programmed Sensor Threshold as shown in Table 6.44. 6.30.1 Lid Closure Threshold 1 Register The Lid Closure Threshold 1 Register controls the lid closure threshold for Capacitive Touch Sensors 1-4. Bits 7-6 - CS4_LD_TH[1:0] - Controls the lid closure threshold for Capacitive Touch Sensor 4. Bits 5-4 - CS3_LD_TH[1:0] - Controls the lid closure threshold for Capacitive Touch Sensor 3. Bits 3-2 - CS2_LD_TH[1:0] - Controls the noise threshold for Capacitive Touch Sensor 2. Bits 1-0 - CS1_LD_TH[1:0] - Controls the noise threshold for Capacitive Touch Sensor 1. 6.30.2 Lid Closure Threshold 2 Register The Lid Closure Threshold 2 Register controls the lid closure threshold for Capacitive Touch Sensors 5 - 8. Bits 7-6 - CS8_LD_TH[1:0] - Controls the lid closure threshold for Capacitive Touch Sensor 8 (one of the grouped sensors). Table 6.43 Lid Closure Threshold Registers ADDR R/W REGISTER B7 B6 B5 B4 B3 B2 B1 B0 DEFAULT 3Ah R/W Lid Closure Threshold 1 CS4_LD_TH [1:0] CS3_LD_TH [1:0] CS2_LD_TH [1:0] CS1_LD_TH [1:0] AAh 3Bh R/W Lid Closure Threshold 2 CS8_LD_TH [1:0] CS7_LD_TH [1:0] CS6_LD_TH [1:0] CS5_LD_TH [1:0] AAh 3Ch R/W Lid Closure Threshold 3 CS12_LD_TH [1:0] CS11_LD_TH [1:0] CS10_LD_TH [1:0] CS9_LD_TH [1:0] AAh 3Dh R/W Lid Closure Threshold 4 -- - - CS14_LD_TH [1:0] CS13_LD_TH [1:0] 0Ah Table 6.44 CSx_LD_TH Bit Decode CSX_LD_TH[1:0] THRESHOLD DIVIDE SETTING 10 0 0 6.25% 01 12.5% 1 0 25% (default) 11 50% |
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