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ML610421 Datasheet(PDF) 26 Page - LAPIS Semiconductor Co., Ltd. |
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ML610421 Datasheet(HTML) 26 Page - LAPIS Semiconductor Co., Ltd. |
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26 / 31 page ![]() FEDL610421-02 ML610421 26/31 AC CHARACTERISTICS (Synchronous Serial Port) (VDD = 1.3 to 3.6V, AVDD = 2.2 to 3.6V, VSS = AVSS = 0V, Ta = −20 to +70°C, unless otherwise specified) Parameter Symbol Condition Rating Unit Min. Typ. Max. SCLK input cycle (slave mode) tSCYC When RC oscillation is active* 2 (VDD = 1.3 to 3.6V) 10 µs When high-speed oscillation is active* 3 (V DD = 1.8 to 3.6V) 1 µs SCLK output cycle (master mode) tSCYC SCLK* 1 s SCLK input pulse width (slave mode) tSW When RC oscillation is active* 2 (VDD = 1.3 to 3.6V) 4 µs When high-speed oscillation is active* 3 (V DD = 1.8 to 3.6V) 0.4 µs SCLK output pulse width (master mode) tSW SCLK* 1 ×0.4 SCLK* 1 ×0.5 SCLK* 1 ×0.6 s SOUT output delay time (slave mode) tSD When RC oscillation is active* 2 (VDD = 1.3 to 3.6V) 500 ns When high-speed oscillation is active* 3 (V DD = 1.8 to 3.6V) 240 SOUT output delay time (master mode) tSD When RC oscillation is active* 2 (VDD = 1.3 to 3.6V) 500 ns When high-speed oscillation is active* 3 (V DD = 1.8 to 3.6V) 240 SIN input setup time (slave mode) tSS 80 ns SIN input setup time (master mode) tSS When RC oscillation is active* 2 (VDD = 1.3 to 3.6V) 500 ns When high-speed oscillation is active* 3 (V DD = 1.8 to 3.6V) 240 SIN input hold time tSH When RC oscillation is active* 2 (VDD = 1.3 to 3.6V) 300 ns When high-speed oscillation is active* 3 (V DD = 1.8 to 3.6V) 80 * 1: Clock period selected with S0CK3–0 of the serial port 0 mode register (SIO0MOD1) * 2: When RC oscillation is selected with OSCM1–0 of the frequency control register (FCON0) * 3: When Crystal/ceramic oscillation, built-in PLL oscillation, or external clock input is selected with OSCM1–0 of the frequency control register (FCON0) tSD SCLK0* SIN0* SOUT0* *: Indicates the secondary function of the port. tSD tSS tSH tSW tSW tSCYC |
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