MCP39F511 datasheet(32/62 Pages) MICROCHIP

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MCP39F511

DS20005393B-page 32

 2015 Microchip Technology Inc.

6.2

Address Pointer Register

This unsigned 16-bit register contains the address to

which all read and write instructions occur. This register

is only written through the Set Address Pointer

command and is otherwise outside the writable range

of register addresses.

6.3

System Status Register

The System Status register is a read-only register and

can be used to detect the various states of pin levels as

defined in Register 6-1.

SYSTEM STATUS REGISTER

U-0

R-x

U-0

—

EVENT2

EVENT1

—

bit 15

bit 8

U-0

R-x

—

OVERTEMP

SIGN_PR

SIGN_PA

OVERPOW

OVERCUR

VSURGE

VSAG

bit 7

bit 0

Legend:

R = Readable bit

W = Writable bit

U = Unimplemented bit, read as ‘0’

-n = Value at POR

‘1’ = Bit is set

‘0’ = Bit is cleared

x = Bit is unknown

bit 15-12

Unimplemented

: Read as ‘0’

bit 11

EVENT2:

State of Event2 Detection algorithm. This bit is latched and must be cleared.

= Event 2 has occurred

= Event 2 has not occurred

bit 10

EVENT1:

State of Event1 Detection algorithm. This bit is latched and must be cleared.

= Event 1 has occurred

= Event 1 has not occurred

bit 9-7

Unimplemented

: Read as ‘0’

bit 6

OVERTEMP

: State of the Overtemperature Detection Algorithm

= Overtemperature Threshold has been broken

= Overtemperature Threshold has not been broken

bit 5

SIGN_PR:

Sign of Reactive Power

= Reactive Power is positive, inductive and is in quadrants 1,2

= Reactive Power is negative, is capacitive and is in quadrants 3,4

bit 4

SIGN_PA:

Sign of Active Power (import/export sign of active power)

= Active Power is positive (import) and is in quadrants 1,4

= Active Power is negative (export) and is in quadrants 2,3

bit 3

OVERPOW:

State of Overpower detection algorithm. An Overpower event has occurred in the system.

= Overpower threshold has been broken

= Overpower threshold has not been broken

bit 2

OVERCUR:

State of the Overcurrent detection algorithm. An Overcurrent event has occurred in the

system.

= Overcurrent threshold has been broken

= Overcurrent threshold has not been broken

bit 1

VSURGE:

State of Voltage Surge Detection algorithm. This bit is latched and must be cleared.

= Surge threshold has been broken

= Surge threshold has not been broken

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