MCP39F511 datasheet(12/62 Pages) MICROCHIP

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MCP39F511

DS20005393B-page 12

 2015 Microchip Technology Inc.

3.1

Event Output Pins (EVENTn)

These digital output pins can be configured to act as

output flags based on various internal raise conditions.

Control is modified through the Event Configuration

3.2

UART Communication Pins

(UART_RX, UART_TX)

The MCP39F511 device contains an asynchronous

full-duplex UART. The UART communication is eight

bits with Start and Stop bit. See Section 4.3 “UART

Settings”

for more information.

3.3

Common Pins (COMMONA and B)

COMMONA and COMMONB pins are internal

connections for the MCP39F511. These two pins

should be connected together in the application.

3.4

Oscillator Pins (OSCI/OSCO)

OSCI and OSCO provide the master clock for the

device. Appropriate load capacitance should be

connected to these pins for proper operation. An

optional 4 MHz crystal can be connected to these pins.

If a crystal of external clock source is not detected, the

device will clock from the internal 4 MHz oscillator.

3.5

Reset Pin (RESET)

This pin is active-low and places the Delta-Sigma

ADCs, PGA, internal VREF and other blocks associated

with the analog front-end in a Reset state when pulled

low. This input is Schmitt-triggered.

3.6

Analog Power Supply Pin (AVDD)

AVDD is the power supply pin for the analog circuitry

within the MCP39F511.

This pin requires appropriate bypass capacitors and

should be maintained to +2.7V and +3.6V for specified

operation. It is recommended to use 0.1 µF ceramic

capacitors.

3.7

Pulse Width Modulator (PWM)

This digital output is a dedicated PWM output that can

be controlled through the PWM Frequency and PWM

Duty Cycle registers. See Section 8.0 “Pulse Width

modulation (PWM)”

for more information.

3.8

24-Bit Delta-Sigma ADC

Differential Current Channel

Input Pins (I1+/I1-)

I1- and I1+ are the two fully-differential current-channel

inputs for the Delta-Sigma ADCs.

The linear and specified region of the channels are

dependent on the PGA gain. This region corresponds

to a differential voltage range of ±600 mVPEAK/GAIN

with VREF =1.2V.

The maximum absolute voltage, with respect to AGND,

for each In+/- input pin is ±1V with no distortion

and ±6V with no breaking after continuous voltage.

3.9

24-Bit Delta-Sigma ADC

Differential Voltage Channel

Inputs (V1-/V1+)

V1-

and

V1+

are

the

two

fully-differential

voltage-channel inputs for the Delta-Sigma ADCs.

The linear and specified region of the channels are

dependent on the PGA gain. This region corresponds

to a differential voltage range of ±600 mVPEAK/GAIN

with VREF =1.2V.

The maximum absolute voltage, with respect to AGND,

for each VN+/- input pin is ±1V with no distortion

and ±2V with no breaking after continuous voltage.

3.10

Analog Input (AN_IN)

This is the input to the analog-to-digital converter that

can be used for temperature measurement and

compensation.

temperature

compensation

required in the application, it is advised to connect the

low-power active thermistor IC MCP9700A to this pin.

If temperature compensation is not required, this can

be used as a general purpose analog-to-digital

converter input.

3.11

Analog Ground Pin (AGND)

AGND is the ground connection to internal analog

circuitry (ADCs, PGA, voltage reference, POR). If an

analog ground pin is available on the PCB, it is

recommended that this pin be tied to that plane.

3.12

Zero Crossing Detection (ZCD)

This digital output pin is the output of the zero crossing

detection circuit of the IC. The output here will be a

logic output with edges that transition at each zero

crossing of the voltage channel input. For more

information

see

Section 5.13

“Zero

Crossing

Detection (ZCD)”

MCP39F511 Datasheet(PDF) 12 Page - Microchip Technology

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