AX8052F131 datasheet(18/29 Pages) ONSEMI

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AX8052F131

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of the old and the new clock. Switching may take longer if

the new oscillator first has to start up. Internal oscillators

start up instantaneously, but crystal oscillators may take a

considerable amount of time to start the oscillation.

CLKSTAT can be read to determine the clock switching

status.

A programmable clock monitor resets the CLKCON

a programmable time interval, thus reverts to the internal RC

oscillator.

Both internal oscillators can be slaved to one of the crystal

oscillators to increase the accuracy of the oscillation

frequency. While the reference oscillator runs, the internal

oscillator is slaved to the reference frequency by a digital

frequency locked loop. When the reference oscillator is

switched off, the internal oscillator continues to run

unslaved with the last frequency setting.

Reset and Interrupts

After reset, the microcontroller starts executing at address

0x0000. Several events can lead to resetting the

microcontroller core:

• POR or hardware RESET_N pin activated and released

• Leaving SLEEP or DEEPSLEEP mode

• Watchdog Reset

• Software Reset

The reset cause can be determined by reading the PCON

The microcontroller supports 22 interrupt sources. Each

interrupt can be individually enabled and can be

programmed to have one of two possible priorities. The

interrupt vectors are located at 0x0003, 0x000B,

…,

0x00AB.

Debugging

A hardware debug unit considerably eases debugging

compared to other 8052 microcontrollers. It allows to

reliably stop the microcontroller at breakpoints even if the

stack is smashed. The debug unit communicates with the

host PC running the debugger using a 3 wire interface. One

wire is dedicated (DBG_EN), while two wires are shared

with GPIO pins (PB6, PB7). When DBG_EN is driven high,

PB6 and PB7 convert to debug interface pins and the GPIO

functionality is no longer available. A pin emulation feature

however allows bits PINB[7:6] to be set and PORTB[7:6]

and DIRB[7:6] to be read by the debugger software. This

allows for example switches or LEDs connected to the PB6,

PB7 pins to be emulated in the debugger software whenever

the debugger is active.

In order to protect the intellectual property of the firmware

developer, the debug interface can be locked using a

developer−selectable 64−bit key. The debug interface is then

disabled and can only be enabled with the knowledge of this

64−bit key. Therefore, unauthorized persons cannot read the

firmware through the debug interface, but debugging is still

possible for authorized persons. Secure erase can be initiated

without key knowledge; secure erase ensures that the main

FLASH array is completely erased before erasing the key,

reverting the chip into factory state.

The DebugLink peripheral looks like an UART to the

microcontroller, and allows exchange of data between the

microcontroller and the host PC without disrupting program

execution.

Timer, Output Compare and Input Capture

The AX8052F131 features three general purpose 16−bit

timers. Each timer can be clocked by the system clock, any

of the available oscillators, or a dedicated input pin. The

timers also feature a programmable clock inversion, a

programmable prescaler that can divide by powers of two,

and an optional clock synchronization logic that

synchronizes the clock to the system clock. All three

counters are identical and feature four different counting

modes, as well as a

SD mode that can be used to output an

analog value on a dedicated digital pin only employing a

simple RC lowpass filter.

Two output compare units work in conjunction with one

of the timers to generate PWM signals.

Two input capture units work in conjunction with one of

the timers to measure transitions on an input signal.

For software timekeeping, two additional 16−bit wakeup

timers with 4 16−bit event registers are provided, generating

an interrupt on match events.

UART

The AX8052F131 features two universal asynchronous

receiver transmitters. They use one of the timers as baud rate

generator. Word length can be programmed from 5 to 9 bits.

SPI Master/Slave Controller

The AX8052F131 features a master/slave SPI controller.

Both 3 and 4 wire SPI variants are supported. In master

mode, any of the on−chip oscillators or the system clock may

be selected as clock source. An additional prescaler with

divide by two capability provides additional clocking

flexibility. Shift direction, as well as clock phase and

inversion, are programmable.

ADC, Analog Comparators and Temperature Sensor

The AX8052F131 features a 10−bit, 500 kSample/s

Analog to Digital converter. Figure 7 shows the block

diagram of the ADC. The ADC supports both single ended

and differential measurements. It uses an internal reference

of 1 V.

×1, ×10 and ×0.1 gain modes are provided. The ADC

may digitize signals on PA0

…PA7, as well as VDD_IO and

an internal temperature sensor. The user can define four

channels which are then converted sequentially and stored

in four separate result registers. Each channel configuration

consists of the multiplexer and the gain setting.

The AX8052F131 contains an on−chip temperature

sensor. Built−in calibration logic allows the temperature

sensor to be calibrated in

°C, °F or any other user defined

temperature scale.

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