AX8052F151 datasheet(22/34 Pages) ONSEMI

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AX8052F151

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AES Engine

The AX8052F151 contains a dedicated engine for the

government mandated Advanced Encryption Standard

(AES). It features a dedicated DMA engine and reads input

data as well as key stream data from the XRAM, and writes

output data into a programmable buffer in the XRAM. The

round number is programmable; the chip therefore supports

AES−128, AES−192, and AES−256, as well as higher

security proprietary variants. Keystream (key expansion) is

performed in software, adding to the flexibility of the AES

engine. ECB (electronic codebook), CFB (cipher feedback)

and OFB (output feedback) modes are directly supported

without software intervention.

Crystal Oscillator (RF Reference Oscillator)

The on−chip crystal oscillator allows the use of an

inexpensive quartz crystal as the RF generation subsystem’s

timing reference. Although a wider range of crystal

frequencies can be handled by the crystal oscillator circuit,

it is recommended to use 16 MHz as reference frequency for

ASK and PSK modulations independent of the data rate. For

FSK it is recommended to use a 16 MHz crystal for data rates

below 200 kbps and 24 MHz for data rates above 200 kbps.

The oscillator circuit is enabled by programming the

AX5051_PWRMODE register. At power−up it is not

enabled.

To adjust the circuit’s characteristics to the quartz crystal

being used, without using additional external components,

both the transconductance and the tuning capacitance of the

crystal oscillator can be programmed.

The transconductance is programmed via register bits

XTALOSCGM[3:0] in register AX5051_XTALOSC.

The integrated programmable tuning capacitor bank

makes it possible to connect the oscillator directly to pins

CLK16N and CLK16P without the need for external

capacitors. It is programmed using bits XTALCAP[5:0] in

To synchronize the receiver frequency to a carrier signal,

the oscillator frequency could be tuned using the capacitor

bank however, the recommended method to implement

frequency synchronization is to make use of the high

resolution RF frequency generation sub−system together

with the Automatic Frequency Control, both are described

further down.

Alternatively a single ended reference (TCXO, CXO)

may be used. The CMOS levels should be applied to

CLK16P via an AC coupling with the crystal oscillator

enabled.

SYSCLK Output

The SYSCLK pin outputs the RF reference clock signal

divided by a programmable integer. Divisions from 1 to

2048 are possible. For divider ratios > 1 the duty cycle is

50%. Bits SYSCLK[3:0] in the AX5051_PINCFG1 register

set the divider ratio. The SYSCLK output can be disabled.

Outputting a frequency that is identical to the IF frequency

(default 1 MHz) on the SYSCLK pin is not recommended

during receive operation, since it requires extensive

decoupling on the PCB to avoid interference.

Power−on−Reset (POR) and RESET_N Input

AX8052F151 has an integrated power−on−reset block

which is edge sensitive to VDD_IO. For many common

application cases no external reset circuitry is required.

However, if VDD_IO ramps cannot be guaranteed, an

external reset circuit is recommended. For detailed

recommendations and requirements see the AX8052

Application Note: Power On Reset.

After POR or reset all registers are set to their default

values.

The RESET_N pin contains a weak pull−up. However, it

is strongly recommended to connect the RESET_N pin to

VDD_IO if not used, for additional robustness.

The AX8052F151 can be reset by software as well. The

microcontroller is reset by writing 1 to the SWRESET bit of

the PCON register. The transmitter can be reset by first

writing 1 and then 0 to the RST bit in the

AX5051_PWRMODE register.

Ports

VDDIO

PORTx.y

DIRx.y

Special Function

PALTx.y

PINx read clock

PINx.y

Interrupt

INTCHGx.y

ANALOGx.y

65 kW

Figure 8. Port Pin Schematic

Figure 8 shows the GPIO logic. The DIR register bit

determines whether the port pin acts as an output (1) or an

input (0).

If configured as an output, the PALT register bit

determines whether the port pin is connected to a peripheral

output (1), or used as a GPIO pin (0). In the latter case, the

PORT register bit determines the port pin drive value.

If configured as an input, the PORT register bit determines

whether a pull−up resistor is enabled (1) or disabled (0).

Inputs have Schmitt−trigger characteristic. Port A inputs

may be disabled by setting the ANALOGA register bit; this

prevents additional current consumption if the voltage level

of the port pin is mid−way between logic low and logic high,

when the pin is used as an analog input.

AX8052F151 Datasheet(PDF) 22 Page - ON Semiconductor

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