PM5347 datasheet(31/302 Pages) PMC

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PM5347 S/UNI-PLUS

DATA SHEET

PMC-941033

ISSUE 6

SATURN USER NETWORK INTERFACE PLUS

PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE

Pin Name

Type

No.

Function

ALOS+

ALOS-

PECL

Input

137

138

The analog loss of signal (ALOS+/-) differential

inputs are used to indicate a loss of receive signal

power. When ALOS+/- is asserted, the data on

the receive data (RXD+/-) pins is forced to all

zeros and the phase locked loop switches to the

reference clock (RRCLK+/-) to keep the recovered

clock in range. These inputs must be DC coupled.

Please refer to the Operation section for a

discussion of PECL interfacing issues.

RATP

Analog

152

This analog test point (RATP) is provided for

production test purposes. Connect this pin to

ground.

LF+,

LF-,

LFO

Analog

151

150

149

Passive components connected to the recovery

loop filter (LF+, LF- and LFO) pins determine the

dynamics of the clock recovery unit. Refer to the

Operation section for details.

TBYP

Input

113

If the transmit bypass (TBYP) input is high,

transmit clock synthesis is disabled and TRCLK+/-

becomes the line rate clock of 155.52 MHz or

51.84 MHz. If TBYP is low, the transmit clock is

synthesized from a 19.44 MHz or 6.48 MHz

reference. TBYP requires an external pull down

resistor.

TRCLK+

TRCLK-

PECL

Input

120

121

The transmit differential reference clock inputs

(TRCLK+, TRCLK-) must be a jitter-free 19.44

MHz or 6.48 MHz reference clock when clock

synthesis is enabled. When clock synthesis is

bypassed, TRCLK+/- is nominally a 155.52 MHz

or 51.84 MHz 50% duty cycle clock. This clock

provides timing for the S/UNI-PLUS transmit

functions. TRCLK+/- may be left unconnected

when S/UNI-PLUS loop timing is enabled, or

when the transmit clock is synthesized from the

receive reference (RRCLK+/-). Please refer to the

Operation section for a discussion of PECL

interfacing issues.

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