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OV7620 Datasheet(PDF) 26 Page - List of Unclassifed Manufacturers

Part # OV7620
Description  OV7620 SINGLE-CHIP CMOS VGA COLOR DIGITAL CAMERA
PDF  60 Pages
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OV7620 Datasheet(HTML) 26 Page - List of Unclassifed Manufacturers

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OV7620 Product Specifications - Rev. 1.2 (5/13/00)
OMNIVISION TECHNOLOGIES INC.
26
Preliminary Company Confidential
1.13 SCCB REGISTER SETS
OV7620 can be configured, by setting pin CS<2:0> high or low at reset/power up, to one of eight
slave IDs as listed below, the ID can not be altered once the chip is out of reset or power up state.
OV7620 support two option: single chip and multiple chip decided by PIN MID. If MID set to
LOW (Default value), chip slave ID is 42(for write) and 43(for read). If MID set to HIGH, OV7620
can support 8 slave ID selection. Default MID is LOW by internal setting.
In write cycle, the second byte in SCCB bus is the subaddress for selecting the individual on chip
registers, the third byte is the data associated with this register. Writing to unimplemented sub-
address and reserved subaddress is ignored.
In read cycle, the second byte is the data associated with the previous stored subaddress. read-
ing of unimplemented subaddress returns unknown.
Registers [00] ~ [02] contains image effect parameters that also can be modified by internal con-
trols in auto adjust mode. This provides a simple way to read out those parameters computed by
chip internal controls. To do this, first set the chip in auto adjust mode (Register 13 bit 0=1, reg-
ister 12 bit 2 = 1, register 12 bit 5=1), wait for the image is stable, the register [00],[01] and [02]
will be updated by internal control circuit. Then returns it to manual adjust mode(register 13 bit
0=0), all the registers retain the last adjusted values and can be read or overwritten by external
host. When the chip is operated in auto adjust mode(register 13 bit 0=1), register [00] ~ [02] will
be update by internal algorithm and if write data to them, there will be no effect on chip parame-
ters. The register data can be read out.
The detailed definitions of each register are described below.
AGC<5:0> - gain setting for the entire image channel.
The formula is:
Gain = (AGC<3:0>/16+1)*(AGC<4>+1)*(AGC<5>+1); range (1x ~ 7.75x), AGC<5> and
AGC<4> control SA2.
Table 1.10: Slave ID
CS<2:0>
000
001
010
011
100
101
110
111
WRITE ID (hex)
42
46
4a
4e
52
56
5a
5e
READ ID (hex)
43
47
4b
4f
53
57
5b
5f
Register 00 - rw: AGC gain control
Bits
Null
AGC6
AGC5
AGC4
AGC3
AGC2
AGC1
AGC0
Default
-
-
0
0
0
0
0
0



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