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OV7620 Datasheet(PDF) 12 Page - List of Unclassifed Manufacturers |
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OV7620 Datasheet(HTML) 12 Page - List of Unclassifed Manufacturers |
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12 / 60 page ![]() OV7620 Product Specifications - Rev. 1.2 (5/13/00) OMNIVISION TECHNOLOGIES INC. 12 Preliminary Company Confidential FIG 1.2 Pixel Data Bus (YUV Output) Note: Tclk is pixel clock period. When OV7620 system clock is 27MHz, Tclk=74ns for 16 Bit out- put; Tclk=37ns for 8 Bit output. Tsu is HREF set-up time, maximum is 15 ns; Thd is HREF hold time, maximum is 15 ns. Y<7:0> PCLK HREF UV<7:0> 10 10 Y Y 80 80 U V repeat for all data bytes Pixel Data 16 bit Timing Y<7:0> PCLK HREF repeat for all data bytes Pixel Data 8 bit Timing U Y V Y 80 10 10 80 Use PCLK rising edge latch data bus Use PCLK rising edge latch data bus Tsu Thd Thd Tclk Tclk 10 Tsu |
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