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OV7620 Datasheet(PDF) 30 Page - List of Unclassifed Manufacturers |
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OV7620 Datasheet(HTML) 30 Page - List of Unclassifed Manufacturers |
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30 / 60 page ![]() OV7620 Product Specifications - Rev. 1.2 (5/13/00) OMNIVISION TECHNOLOGIES INC. 30 Preliminary Company Confidential . COMA7 - “1” initiates the chip soft reset, the reset takes place after the acknowledge bit is issued, the effect is the same as power up the chip, the chip is initialized to a default state, all registers including SCCB’s contents are set to default, this bit is self cleared after the reset. COMA6 - “1” selects mirror image COMA5 - “1” enables AGC. “0” - stop AGC and set register [00] to default value. Only effective in auto adjust mode. COMA4 - “1” select 8 Bit Digital output format is Y U Y V Y U Y V ... COMA3 - “1” selects raw data signal as video data output, “0” selects YCrCb as video data output. The selection applies to both analog video and digital video. COMA2 - “1” enable auto white balance, “0” AWB stop and AWB register [01] and [02] value is held at last updated value. Can used as one-shot AWB mode. Valid only in auto mode. COMA1 - “1” selects Color Bar Test pattern output. COMA0 - “1” select precise A/D Black Level Compensation (BLC) line method. “0” use standard black level compensation to do A/D BLC field method which is more stable but less precise. COMB7 - Reserved. COMB6 - Reserved. COMB5 - “1” selects 8 bit data format, Y/CrCb and RGB video data is multiplexed to the eight bit Y bus, tri- state UV bus; “0” selects 16 bit format, data go to both Y<7:0> bus and UV<7:0> bus. COMB4 - “0” enables digital output in CCIR601 format. “1” enables CCIR656 format. COMB3 - “0” selects horizontal sync for output to pin CHSYNC, “1” selects composite sync for output. COMB2 - “1” tri-states bus Y<7:0> and UV<7:0>, “0” enables both buses. COMB1 - “1” initiates the single frame transfer, for this function to work, field drop mode (FD<1:0> in regis- ter [16]) must set to “OFF”. See figure below. After this bit is set, for Interlaced mode, HREF is only asserted for consecutive two fields beginning at Odd field. This bit is cleared automati- cally at the end of this frame. For Progressive Scan mode, HREF is only asserted for one frame. Clearing this bit in the middle of active frame has no effect to the assertion of current HREF. COMB0 - “1” enables auto adjust mode, in this mode, internal exposure circuitry overwrites those parame- ters in registers [00]~[02], the chip adjusts the image based on a preset algorithm. “0” manual adjust mode. Register 12 - rw: Common control A Bits COMA7 COMA6 COMA5 COMA4 COMA3 COMA2 COMA1 COMA0 Default 0 0 1 0 0 1 0 0 Register 13 - rw: Common control B Bits COMB7 COMB6 COMB5 COMB4 COMB3 COMB2 COMB1 COMB0 Default - - 0 0 0 0 0 1 |
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