LAN9211 datasheet(103/147 Pages) SMSC

103 / 147 page

High-Performance Small Form Factor Single-Chip Ethernet Controller with HP Auto-MDIX Support

Datasheet

SMSC LAN9211

103

Revision 2.9 (03-01-12)

DATASHEET

5.3.24

E2P_DATA – EEPROM Data Register

This register is used in conjunction with the E2P_CMD register to perform read and write operations

with the Serial EEPROM.

EPC Time-out. If an EEPROM operation is performed, and there is no

response from the EEPROM within 30mS, the EEPROM controller will time-

out and return to its idle state. This bit is set when a time-out occurs

indicating that the last operation was unsuccessful.

Note:

If the EEDIO signal pin is externally pulled-high, EPC commands

will not time out if the EEPROM device is missing. In this case the

EPC Busy bit will be cleared as soon as the command sequence

is complete. It should also be noted that the ERASE, ERAL,

WRITE and WRAL commands are the only EPC commands that

will time-out if an EEPROM device is not present -and- the EEDIO

signal is pulled low

R/WC

MAC Address Loaded. When set, this bit indicates that a valid EEPROM

was found, and that the MAC address programming has completed

normally. This bit is set after a successful load of the MAC address after

power-up, or after a RELOAD command has completed

R/WC

7-0

EPC Address. The 8-bit value in this field is used by the EEPROM

Controller to address the specific memory location in the Serial EEPROM.

This is a Byte aligned address.

R/W

00h

Offset:

B4h

Size:

32 bits

BITS

DESCRIPTION

TYPE

DEFAULT

31-8

Reserved

7:0

EEPROM Data. Value read from or written to the EEPROM.

R/W

00h

BITS

DESCRIPTION

TYPE

DEFAULT

LAN9211 Datasheet(PDF) 103 Page - SMSC Corporation

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