AMS4123 datasheet(14/18 Pages) ADMOS

14 / 18 page

AMS4123

3A 20V Step-Down Converter + 1A LDO

3/5/2010

www.advanced-monolithic.com

Phone (925) 443-0722

Fax (925) 443-0723

PCB Layout

The following guidelines should be followed to insure

proper layout.

1. Vin Capacitor. A low ESR ceramic bypass

capacitor must be placed as close to the IC as

possible.

2. Schottky Diode. During the off portion of the

switching cycle the inductor current flows through

the Schottky diode to the output cap and returns

to the inductor through the output capacitor. The

trace that connects the output diode to the output

capacitor sees a current signal with a very high

di/dt. To minimize the associated spiking and

ringing, the inductance and resistance of this

trace should be minimized by connecting the

diode anode to the output capacitor return with a

short wide trace.

3. Feedback Resistors. The feedback resistors

should be placed as close as possible the IC.

Minimize the length of the trace from the feedback

pin to the resistors. This is a high impedance

node susceptible to interference from external RF

noise sources.

4. Inductor. Minimize the length of the SW node

trace. This minimizes the radiated EMI associated

with the SW node.

5. Ground. The most quiet ground or return potential

available is the output capacitor return. The

inductor

current

flows

through

the

output

capacitor during both the on time and off time,

hence it never sees a high di/dt. The only di/dt

seen by the output capacitor is the inductor ripple

current which is much less than the di/dt of an

edge to a square wave current pulse. This is the

best place to make a solid connection to the IC

ground and input capacitor. This node is used as

the star ground shown in Figure 1. This method of

grounding helps to reduce high di/dt traces, and

the detrimental effect associated with them, in a

step-down converter. The inductance of these

traces should always be minimized by using wide

traces, ground planes, and proper component

placement.

6. For good thermal performance vias are required

to couple the exposed tab of the SO-8 package to

the PCB ground plane. The via diameter should

be 0.3mm to 0.33mm positioned on a 1.2mm grid.

Figure 1. Step Down Converter Layout

Ion

Ioff

Ion+ Ioff

Ion

Ioff

Ion+Ioff

High

di/dt

PCB Inductance

Ion

Ioff

High di/dt trace reduction

“Star Ground”

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