TMS28F210 datasheet(18/25 Pages) TI

18 / 25 page

TMS28F210

65536 BY 16-BIT

FLASH MEMORY

SMJS210D – DECEMBER 1992 – REVISED AUGUST 1997

POST OFFICE BOX 1443

• HOUSTON, TEXAS 77251–1443

timing requirements — alternative E-controlled writes

ALTERNATE

’28F210 10

’28F210 12

’28F210 15

’28F210 17

ALTERNATE

’28F210 - 10

’28F210 - 12

’28F210 - 15

’28F210 - 17

UNIT

SYMBOL

MIN

MAX

MIN

MAX

MIN

MAX

MIN

MAX

UNIT

tc(W)

Cycle time, write using E

tAVAV

100

120

150

170

tc(E)PR

Cycle time, programming

operation

tEHEH

µs

th(EA)

Hold time, address

tELAX

th(ED)

Hold time, data

tEHDX

th(W)

Hold time, W

tEHWH

tsu(A)

Setup time, address

tAVEL

tsu(D)

Setup time, data

tDVEH

tsu(W)

Setup time, W before E

tWLEL

tsu(VPPEL) Setup time, VPP to E low

tVPEL

µs

trec(E)R

Recovery time, write using E

before read

tEHGL

µs

trec(E)W

Recovery time, read before

write using E

tGHEL

µs

tw(E)

Pulse duration, write using E

tELEH

tw(EH)

Pulse duration, write, E high

tEHEL

PARAMETER MEASUREMENT INFORMATION

2.08 V

CL = 100 pF

(see Note A)

Output

Under Test

RL = 800 Ω

2.4 V

0.45 V

2 V

0.8 V

2 V

0.8 V

LOAD CIRCUIT

VOLTAGE WAVEFORMS

NOTES: A. CL includes probe and fixture capacitance.

B. AC testing inputs are driven at 2.4 V for logic high

and 0.45 V for logic low. Timing measurements

are

made

for

logic

high

and

0.8 V for logic low on both inputs and outputs.

Each device should have a 0.1-

µF ceramic

capacitor connected between VCC and VSS as

close as possible to the device pins.

Figure 4. Load Circuit and Voltage Waveforms

TMS28F210 Datasheet(PDF) 18 Page - Texas Instruments

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