TPS22933

SLVSB34A – OCTOBER 2011 – REVISED JUNE 2015

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6.2 ESD Ratings

VALUE

UNIT

±2000

Electrostatic discharge

V

Charged-device model (CDM), per JEDEC specification JESD22-

±1000

(1)

JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. Manufacturing with

less than 500-V HBM is possible with the necessary precautions. Pins listed as ±2000 V may actually have higher performance.

(2)

JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process. Manufacturing with

less than 250-V CDM is possible with the necessary precautions. Pins listed as ±1000 V may actually have higher performance.

6.3 Recommended Operating Conditions

MIN

NOM

MAX

UNIT

BAT, USB, DC_IN

2.5

12

V

Input voltage

EN

0

5.5

V

EN pin High-level input voltage,

BAT = 2.5 V to 5.5 V, USB, DC_IN = 2.5 V to 12

1.15

5.5

V

V

Output)

EN pin Low-level input voltage,

BAT = 2.5 V to 5.5 V, USB, DC_IN = 2.5 V to 12

0

0.6

V

V

LOUT Current

50

mA

VOUT Current

50

mA

LOUT + VOUT current

50

mA

EN = 3.4 V

LDO Capacitor (on CAP pin)

nF

CAP

LOUT Capacitor

1

µF

VOUT Capacitor

1

µF

(1)

Refer to Application and Implementation.

6.4 Thermal Information

TPS22933

RSE (UQFN)

UNIT

6 PINS

Junction-to-ambient thermal resistance

115.6

°C/W

Junction-to-case (top) thermal resistance

59.9

°C/W

Junction-to-board thermal resistance

27.4

°C/W

Junction-to-top characterization parameter

2.1

°C/W

Junction-to-board characterization parameter

27.3

°C/W

Junction-to-case (bottom) thermal resistance

—

°C/W

(1)

For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application

report, SPRA953.

4

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