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HMC704LP4E Datasheet(PDF) 39 Page - Analog Devices

Part # HMC704LP4E
Description  8 GHZ FRACTIONAL-N PLL
PDF  44 Pages
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Manufacturer  AD [Analog Devices]
Direct Link  http://www.analog.com
Logo AD - Analog Devices

HMC704LP4E Datasheet(HTML) 39 Page - Analog Devices

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HMC704LP4E
v04.0215
8 GHZ FRACTIONAL-N PLL
For price, delivery and to place orders: Analog Devices, Inc., One Technology Way, Norwood, MA 02062
978-250-3343 tel • 978-250-3373 fax • Order online at www.analog.com/hittitemw
Application support: Phone: 978-250-3343 or RFMG-apps@analog.com
Table 20. Reg 07h Lock Detect Register
BIT
TYPE
NAME
W
DEFLT
DEsCRIPTION
[2:0]
R/W
lkd_wincnt_max
3
5
Lock Detect window sets the number of consecutive counts of
divided VCO that must land inside the Lock Detect Window to
declare LOCK
0: 5
1: 32
2: 96
3: 256
4: 512
5: 2048
6: 8192
7: 65535
[3]
R/W
Enable Internal Lock Detect
1
1
Enable Internal Lock Detect
[5:4]
R/W
Reserved
2
0
Reserved
[6]
R/W
Lock Detect Window type
1
0
Lock Detection Window Timer selection
1: Digital programmable timer
0: Analog one shot, nominal +/-10nsec window
[9:7]
R/W
LD Digital Window duration
3
0
Lock Detection - Digital Window Duration
0: 1/2 cycle
1: 1 cycle
2: 2 cycles
3: 4 cycles
4: 8 cycles
5: 16 cycles
6: 32 cycles
7: 64 cycles
[11:10]
R/W
LD Digital Timer Freq Control
2
0
Lock Detect Digital Timer Frequency Control
“00” fastest “11” slowest
[12]
R/W
LD Timer Test Mode
1
0
1: Force Timer ON Continuously - For Test Only
0: Normal Timer operation - one shot
[13]
R/W
Auto Relock - One Try
1
0
1: Attempts to relock if Lock Detect fails for any reason
Only tries once.
Table 21. Reg 08h Analog EN Register
BIT
TYPE
NAME
W
DEFLT
DEsCRIPTION
0
R/W
bias_en
1
1
Enables main chip bias reference. Program 1b
1
R/W
cp_en
1
1
Charge pump enable Program 1b
2
R/W
pd_en
1
1
PD enable Program 1b
3
R/W
refbuf_en
1
Reference path buffer enable Program 1b
4
R/W
vcobuf_en
1
1
VCO path RF buffer enable Program 1b
5
R/W
GPO/LDO/sDO_pad_en
1
1
0 - Pin LD_sDO disabled
1 - and Reg0Fh[7]=1, Pin LD_sDO is always on (required to output
LD state or view GPO signals).
1 - and Reg0Fh[7]=0, Pin LD_sDO only outputs sDO data provided
Reg0Fh[6]=0.
6
R/W
Reserved
1
1
Program 1b
7
R/W
VCO_Div_Clk_to_dig_en
1
1
VCO Divider Clock to Digital Enable Program 1b
8
R/W
Reserved
1
0
Program 0
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.
For price, delivery, and to place orders: Analog Devices, Inc.,
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106
Phone: 781-329-4700 • Order online at www.analog.com
Application Support: Phone: 1-800-ANALOG-D



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