HMC704LP4E datasheet(43/44 Pages) AD

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HMC704LP4E

v04.0215

8 GHZ FRACTIONAL-N PLL

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978-250-3343 tel • 978-250-3373 fax • Order online at www.analog.com/hittitemw

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Table 25. Reg 0Ch Exact Frequency Register

BIT

TYPE

NAME

DEFLT

DEsCRIPTION

[13:0]

R/W

Number of Channels per Fpd

Comparison Frequency divided by the channel spacing. Must be an

integer. Frequencies at multiples of the channel spacing will have

zero frequency error. Only works in modulator Mode B. Must be 0

otherwise

0: Disabled

1: Disabled

2 to 16383d (3FFFh) allowed

Table 26. Reg 0Fh GPO Register

BIT

TYPE

NAME

DEFLT

DEsCRIPTION

[4:0]

R/W

gpo_select

signal selected here is output to sDO pin when enabled

0. Data from Reg0F[5]

1. Lock Detect Output

2. Lock Detect Trigger

3: Lock Detect Window Output

4: Ring Osc Test

5. Pullup Hard from CsP

6. PullDN hard from CsP

7. Reserved

8: Reference Buffer Output

9: Ref Divider Output

10. VCO divider Output

11. Modulator Clock from VCO divider

12. Auxiliary Clock

13. Aux sPI Clock

14. Aux sPI Enable

15. Aux sPI Data Out

16. PD DN

17. PD UP

18. sD3 Clock Delay

19. sD3 Core Clock

20. Autostrobe Integer Write

21. Autostrobe Frac Write

22. Autostrobe Aux sPI

23. sPI Latch Enable

24. VCO Divider sync Reset

25. seed Load strobe

26.-29 Not Used

30. sPI Output Buffer En

31. soft RsTB

[5]

R/W

GPO Test Data

1 - GPO Test Data when GPO_select = 0

[6]

R/W

Prevent Automux sDO

1- inhibits Automux of the sPI sDO line with Lock Detect

[7]

R/W

Prevent Driver Disable

1- Prevents sPI from disabling sDO. should be 1 if using HMC sPI

mode.

[8]

R/W

Disable PFET

[9]

R/W

Disable NFET

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One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106

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