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HMC704LP4E Datasheet(PDF) 19 Page - Analog Devices

Part # HMC704LP4E
Description  8 GHZ FRACTIONAL-N PLL
PDF  44 Pages
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Manufacturer  AD [Analog Devices]
Direct Link  http://www.analog.com
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HMC704LP4E Datasheet(HTML) 19 Page - Analog Devices

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HMC704LP4E
v04.0215
8 GHZ FRACTIONAL-N PLL
For price, delivery and to place orders: Analog Devices, Inc., One Technology Way, Norwood, MA 02062
978-250-3343 tel • 978-250-3373 fax • Order online at www.analog.com/hittitemw
Application support: Phone: 978-250-3343 or RFMG-apps@analog.com
Ref Path ’R’ Divider
The reference path “R” divider is based on a 14 bit counter and can divide input signals of up to 350 MHz input by values
from 1 to 16,383 and is controlled by “Reg 02h”[13:0]. The reference divider output may be viewed in test mode on the
LD_sDO pin, by setting “Reg 0Fh”[4:0] = 9d.
RF Path
The RF path is shown in Figure 28. This path features a low noise 8 GHz RF input buffer followed by an 8GHz RF divide-
by-2 with a selectable bypass. If the VCO input is below 4 GHz the RF divide-by-2 should be by-passed for reduced
power consumption and improved performance in fractional mode. The RF divide-by-2 is followed by the N divider, a 19
bit divider that can operate in either integer or fractional mode with up to 4 GHz inputs. Finally the N divider is followed
by the Phase Detector (PD), which has two inputs, the RF path from the VCO (V) and the reference path (R) from the
crystal. The PD can operate at speeds up to 80 MHz in fractional Mode A, 100 MHz in fractional Mode B and 115 MHz in
integer mode.
RF Input Stage
The RF input stage provides the path from the external VCO to the phase detector via the RF or ’N’ divider. The RF input
path is rated to operate up to 8 GHz across all conditions. The RF input stage is a differential common emitter stage with
internal DC bias, and is protected by EsD diodes as shown in Figure 29. This input is not matched to 50 Ohms. A 50
Ohm resistor placed across the inputs can be used if desired. In most applications the input is used single-ended into
either the VCOIP or VCOIN pin with the other input connected to ground through a DC blocking capacitor. The preferred
input level for best spectral performance is -10 dBm nominally.
Figure 29. RF Input Stage
Figure 28. RF Path
RF Buffer
/2 or
8GHz
8GHz
4GHz
Bypass
19 Bit /N
PD
80MHz/100MHz Fractional
115MHz Integer
V
R
Ref Path
sEL
CONTROL
VCOIP
VCOIN
RF Divide by 2 N Divider
Phase Detector
CP
UP
DN
CP
VPPCP
Charge Pump
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.
For price, delivery, and to place orders: Analog Devices, Inc.,
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106
Phone: 781-329-4700 • Order online at www.analog.com
Application Support: Phone: 1-800-ANALOG-D



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