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AD5671R Datasheet(PDF) 23 Page - Analog Devices |
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AD5671R Datasheet(HTML) 23 Page - Analog Devices |
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23 / 32 page  Data Sheet AD5671R/AD5675R Rev. B | Page 23 of 32 SERIAL INTERFACE The AD5671R/AD5675R use a 2-wire, I2C-compatible serial interface. These devices can be connected to an I2C bus as a slave device under the control of the master devices. The AD5671R/AD5675R support standard (100 kHz) and fast (400 kHz) data transfer modes. Support is not provided for 10-bit addressing and general call addressing. Input Shift Register The input shift register of the AD5671R/AD5675R is 24 bits wide. Data is loaded MSB first (DB23), and the first four bits are the command bits, C3 to C0 (see Table 9), followed by the 4-bit DAC address bits, A3 to A0 (see Table 10), and finally, the bit data-word. The data-word comprises 16-bit or 12-bit input code, followed by zero or four don’t care bits for the AD5675R and AD5671R, respectively (see Figure 58 and Figure 59). These data bits are transferred to the input register on the 24 falling edges of SCL. Commands execute on individual DAC channels, combined DAC channels, or on all DACs, depending on the address bits selected. Table 9. Command Definitions Command C3 C2 C1 C0 Description 0 0 0 0 No operation 0 0 0 1 Write to Input Register n (dependent on LDAC) 0 0 1 0 Update DAC Register n with contents of Input Register n 0 0 1 1 Write to and update DAC Channel n 0 1 0 0 Power down/power up DAC 0 1 0 1 Hardware LDAC mask register 0 1 1 0 Software reset (power-on reset) 0 1 1 1 Internal reference and gain setup register 1 0 0 0 Reserved 1 0 0 1 Reserved 1 0 1 0 Update all channels of input register simultaneously with the input data 1 0 1 1 Update all channels of DAC register and input register simultaneously with the input data 1 1 0 0 Reserved … … … … 1 1 1 1 Reserved Table 10. Address Commands Channel Address[3:0] Selected Channel1 A3 A2 A1 A0 0 0 0 0 DAC 0 0 0 0 1 DAC 1 0 0 1 0 DAC 2 0 0 1 1 DAC 3 0 1 0 0 DAC 4 0 1 0 1 DAC 5 0 1 1 0 DAC 6 0 1 1 1 DAC 7 1 Any combination of DAC channels can be selected using the address bits. Figure 58. AD5675R Input Shift Register Content Figure 59. AD5671R Input Shift Register Content DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 C3 C2 C1 C0 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 COMMAND DAC ADDRESS DAC DATA DAC DATA COMMAND BYTE DATA HIGH BYTE DATA LOW BYTE A3 A2 A1 A0 DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 C3 C2 C1 C0 A3 A2 A1 A0 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 X X X X COMMAND DAC ADDRESS DAC DATA DAC DATA COMMAND BYTE DATA HIGH BYTE DATA LOW BYTE |
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