PCI7421 datasheet(189/298 Pages) TI

189 / 298 page

8−9

8.9

Bus Options Register

The bus options register externally maps to the second quadlet of the Bus_Info_Block. See Table 8−7 for a complete

description of the register contents.

Bit

Name

Bus options

Type

Default

Bit

Name

Bus options

Type

Default

Bus options

Offset:

20h

Type:

Read/Write, Read-only

Default:

X0XX A0X2h

Table 8−7. Bus Options Register Description

BIT

FIELD NAME

TYPE

DESCRIPTION

irmc

Isochronous resource-manager capable. IEEE 1394 bus-management field. Must be valid when bit 17

(linkEnable) in the host controller control register at OHCI offset 50h/54h (see Section 8.16) is set to 1.

The default value for this bit is 0.

cmc

Cycle master capable. IEEE 1394 bus-management field. Must be valid when bit 17 (linkEnable) in the

host controller control register at OHCI offset 50h/54h (see Section 8.16) is set to 1. The default value for

this bit is 0.

isc

Isochronous support capable. IEEE 1394 bus-management field. Must be valid when bit 17 (linkEnable)

in the host controller control register at OHCI offset 50h/54h (see Section 8.16) is set to 1. The default

value for this bit is 0.

bmc

Bus manager capable. IEEE 1394 bus-management field. Must be valid when bit 17 (linkEnable) in the

host controller control register at OHCI offset 50h/54h (see Section 8.16) is set to 1. The default value for

this bit is 0.

pmc

Power-management capable. IEEE 1394 bus-management field. When bit 27 is set to 1, this indicates that

the node is power-management capable. Must be valid when bit 17 (linkEnable) in the host controller

control register at OHCI offset 50h/54h (see Section 8.16) is set to 1. The default value for this bit is 0.

26−24

RSVD

Reserved. Bits 26−24 return 0s when read.

23−16

cyc_clk_acc

Cycle master clock accuracy, in parts per million. IEEE 1394 bus-management field. Must be valid when

bit 17 (linkEnable) in the host controller control register at OHCI offset 50h/54h (see Section 8.16) is set

to 1. The default value for this field is 00h.

15−12 ‡

max_rec

Maximum request. IEEE 1394 bus-management field. Hardware initializes this field to indicate the

maximum number of bytes in a block request packet that is supported by the implementation. This value,

max_rec_bytes, must be 512 or greater, and is calculated by 2^(max_rec + 1). Software may change this

field; however, this field must be valid at any time bit 17 (linkEnable) in the host controller control register

at OHCI offset 50h/54h (see Section 8.16) is set to 1. A received block write request packet with a length

greater than max_rec_bytes may generate an ack_type_error. This field is not affected by a software reset,

and defaults to value indicating 2048 bytes on a system (hardware) reset. The default value for this field

is Ah.

11−8

RSVD

Reserved. Bits 11−8 return 0s when read.

7−6

Generation counter. This field is incremented if any portion of the configuration ROM has been

incremented since the prior bus reset.

5−3

RSVD

Reserved. Bits 5−3 return 0s when read.

2−0

Lnk_spd

Link speed. This field returns 010, indicating that the link speeds of 100M bits/s, 200M bits/s, and

400M bits/s are supported.

‡ These bits are cleared only by the assertion of GRST.

PCI7421 Datasheet(PDF) 189 Page - Texas Instruments

PCI7421 Datasheet(HTML) 189 Page - Texas Instruments

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL