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AD7725 Datasheet(PDF) 5 Page - Analog Devices |
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AD7725 Datasheet(HTML) 5 Page - Analog Devices |
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5 / 28 page  REV. A AD7725 –5– Parameter Symbol Min Typ Max Unit CLKIN Frequency f CLKIN 114.4 MHz CLKIN Period (t CLK = 1/fCLKIN)t1 0.07 1 µs CLKIN Low Pulse Width t 2 0.45 t 1 0.55 t 1 CLKIN High Pulse Width t 3 0.45 t 1 0.55 t 1 CLKIN Rise Time t 4 5ns CLKIN Fall Time t 5 5ns CLKIN to SCO Delay t 6 35 50 ns SCO Period: SCR = 0 t 7 1t CLK SCR = 1 t 7 2t CLK SERIAL INTERFACE (DSP MODE ONLY) FSI Setup Time before SCO Transition t 8 30 ns FSI Hold Time after SCO Transition t 9 0ns SDI Setup Time t 10 30 ns SDI Hold Time t 11 0ns SERIAL INTERFACE (DSP AND BFR MODES) SCO Transition to FSO High Delay t 12 20 ns SCO Transition to FSO Low Delay t 13 20 ns SDO Setup before SCO Transition t 14 10 ns SDO Hold after SCO Transition t 15 0ns SERIAL INTERFACE (EPROM MODE) SCO High Time t 16 8t CLK SCO Low Time t 17 8t CLK SOE Low to First SCO Rising Edge t 18 20 t CLK Data Setup before SCO Rising Edge t 19 22 ns PARALLEL INTERFACE DATA WRITE RS Low to CS Low t 20 15 ns WR Setup before CS Low t 21 15 ns RS Hold after CS Rising Edge t 22 0ns CS Pulse Width t 23 50 ns WR Hold after CS Rising Edge t 24 0ns Data Setup Time t 25 10 ns Data Hold Time t 26 5ns DATA READ RS Low to CS Low t 27 15 ns RD Setup before CS Low t 28 15 ns RS Hold after CS Rising Edge t 29 0ns RD Hold after CS Rising Edge t 30 0ns Data Valid after CS Falling Edge3 t 31 30 ns Data Hold after CS Rising Edge t 32 10 ns STATUS READ/INSTRUCTION WRITE CS Duty Cycle t 33 1t CLK Interrupt Clear after CS Low t 34 15 ns RD Setup to CS Low t 35 15 ns RD Hold after CS Rising Edge t 36 0ns Read Data Access Time 3 t 37 30 ns Read Data Hold after CS Rising Edge t 38 10 ns Write Data Setup before CS Rising Edge t 39 10 ns Write Data Hold after CS Rising Edge t 40 5ns NOTES 1Guaranteed by design. 2Guaranteed by characterization. All input signals are specified with tr tf 5 ns (10% to 90% of DV DD) and timed from a voltage level of 1.6 V. 3Measured with the load circuit in Figure 2 and defined as the time required for the output to cross 0.8 V and 2.4 V. TIMING SPECIFICATIONS1, 2 (AVDD = 5 V 5%; DV DD = 5 V 5%; AGND = DGND = 0 V, REF2 = 2.5 V, unless otherwise noted.) |
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