REV. A

AD7725

–9–

PIN CONFIGURATION

3

4

5

6

7

1

2

10

11

8

9

40 39 38

41

42

43

44

36 35 34

37

29

30

31

32

33

27

28

25

26

23

24

PIN 1

IDENTIFIER

TOP VIEW

(Not to Scale)

12 13 14 15 16 17 18 19 20 21 22

SCR/DB13

SMODE0/DB14

SMODE1/DB15

SOE/CS

SYNC

DGND

STBY

AD7725

EFMT/DB2

ERR/DB1

SDI/DB0

CFMT/RS

DVAL/INT

DGND

RD/

WR

S/

P

AGND1

AGND1

AGND

UNI

REF2

PIN FUNCTION DESCRIPTIONS

Pin No.

Mnemonic S/P

Description

1

EFMT/DB2

Serial Mode. EFMT–Serial Clock Format, Logic Input. This clock format pin selects

the clock edge to be used during configuration. When EFMT is low, Serial Data In is

valid on the rising edge of SCO; when EFMT is high, Serial Data In is valid

on the falling edge of SCO. During normal operation, this pin is ignored.

Parallel Mode. DB2–Data Input/Output Bit.

2

ERR/DB1

Serial Mode.

ERR–Configuration Error Flag, Logic Output. If an error occurs during

configuration, this output goes low and is reset high by a pulse on the

RESETCFG pin.

Parallel Mode. DB1–Data Input/Output Bit.

3

SDI/DB0

Serial Mode. SDI–Serial Data Input. Serial data is shifted in to the AD7725 MSB first, in

twos complement format, synchronous with SCO.

Parallel Mode. DB0–Data Input/Output Bit (LSB).

4

CFMT/RS

Serial Mode. CFMT–Serial Clock Format, Logic Input. This clock format pin selects the

clock edge to be used during normal operation. When CFMT is low, Serial Data Out is

valid on the rising edge of SCO; when CFMT is high, Serial Data Out is valid on the

falling edge of SCO. During configuration, this pin is ignored.

Parallel Mode. RS–Register Select. RS selects between the data register, used to read

conversion data or write configuration data, and the instruction register. When RS is high,

the status register can be read or an instruction can be written to the AD7725. When RS

is low, data such as the configuration file can be written to the ADC while data such as the

device ID or a conversion result can be read from the AD7725 (see Table I).