AD7725 datasheet(24/28 Pages) AD

24 / 28 page

REV. A

–24–

AD7725

Table IV. Programming Modes

SMODE[1, 0]

Configuration Mode

Description

0xx

PARALLEL

Parallel Interface. The 16-bit bidirectional microprocessor.

Interface is used for read/write operations.

100

BFR

Serial Interface. Boot from the default filter (internal ROM) at

power-on reset (POR).

101

DSP

Serial Interface. Bidirectional serial synchronous interface

suitable for interfacing to a DSP.

110

EPROM

Serial Interface. Boot from external serial EPROM at POR.

111

EPROM

Serial Interface. Boot from external serial EPROM at POR.

EPROM Mode—Loading Configuration Data from an

External EPROM

In this mode, a user-defined filter can be developed off-chip, and

the resulting configuration file is loaded into the postprocessor in

the AD7725 from an External EPROM. The AD7725 therefore

receives filter data from an EPROM before outputting conversion

results via the serial interface to a DSP. This mode of operation is

selected by tying SMODE0 to DGND and SMODE1 to DVDD.

The values on these pins inform the AD7725 that user-defined

filter data is to be loaded from an external EPROM automatically

on power-up. Following power-up, the AD7725 will drive the

SOE

pin low, which will enable the EPROM and reset its address

counter. The transfer of the configuration data will then com-

mence with the data being latched into the AD7725 on the SCO

rising edge. During the download of data, SCO has a frequency of

CLKIN/16. FSI is not used in the data transfer, so it should be tied

low. Once configuration is complete and no error occurred,

SOE

will go high, disabling the EPROM; SCO will return to either

CLKIN or CLKIN/2, depending on SCR; CFGEND will go high

driving the INIT pin high, and the device will start converting.

However, if an error does occur during the configuration, the

ERR

bit will go low and CFGEND will not go high. The part will not

do anything until

RESETCFG is pulsed low. When this occurs,

the part is reset,

SOE goes low again to enable the EPROM,

and the part is reconfigured. Figure 28 shows the connection

diagram for the AD7725 when loading configuration data from

an EPROM, and Figure 29 shows a flow chart of the power-up

and configuration sequence.

DVDD

ERR

DVAL

INIT

RESETCFG

CFGEND

SMODE0

SYNC

SCO

FSO

SDO

FSI

AD7725

SCLK0

RFS0

DR0

ADSP-21xx

SMODE1

SERIAL EPROM

DVDD

SDI

SOE

Figure 28. Connection Diagram for Loading the

Filter Configuration Data from an External EPROM

POWER-ON RESET

IMMEDIATE BOOT

FROM AN EPROM

USER-DEFINED FILTER

DATA LOADED INTO

THE POSTPROCESSOR

FROM EPROM

SOE GOES HIGH

CFGEND = 1

INIT = 1

DEVICE STARTS

CONVERTING

SMODE0 = 0

SMODE1 = 1

DATA

LOADED

CORRECTLY?

PULSE

RESETCFG

LOW

YES

ERR = 0

SOE GOES LOW

Figure 29. Flow Chart of EPROM Mode

Boot from ROM Mode (BFR)—Using the Internal

Default Filter

This mode of operation allows the user to evaluate the AD7725

without having to load configuration data. It is selected by tying

SMODE0 and SMODE1 to DGND. The values on these pins

inform the AD7725 that the postprocessor is to be configured

with the default filter stored in internal ROM. The default filter

data will be loaded into the postprocessor automatically following

power-up. Once the configuration is complete, the CFGEND pin

will go high. In Figure 30, CFGEND is tied to INIT, thus it will

drive the INIT pin high, and the AD7725 will begin converting.

FSI and SDI are not used in this mode, so they should be tied

to DGND. In this mode of operation, the AD7725 operates as a

normal

ADC with a fixed filter response.

During configuration, SCO will have a frequency of CLKIN/16.

Once configuration is complete, the frequency of SCO is selected

by SCR and will be either CLKIN or CLKIN/2. Additionally,

the SCO edge on which the data is output from the device can

be selected using CFMT. With SCR = 0, SCO equals CLKIN.

With SCR = 1, SCO equals CLKIN/2. With CFMT = 0, data is

output on the SCO rising edge, while data is output on the

falling edge when CFMT = 1. Figure 30 shows the connection

diagram for the AD7725 when using the internal default filter,

and Figure 31 shows a flow chart of the power-up and configu-

ration sequence.

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