AD7725 datasheet(23/28 Pages) AD

23 / 28 page

REV. A

AD7725

–23–

Converting

To begin conversions, the RdCONV (Read Converter Data)

instruction is issued (see Table III). INT is asserted as soon as

the conversion data is ready to be read (Bit 14 of the status

read from the device. It will then go low and return high when

the next conversion is complete. The device continues to con-

vert until the ABORT instruction is issued.

SERIAL MODE

The serial mode is selected by tying S/

P to DV

DD. Figure 4

shows the serial interface of the AD7725. The AD7725 operates

solely as a master providing two serial data input pins for the

transfer of configuration data into the device (FSI and SDI),

two serial data output pins for transfer of conversion data out of

the device (FSO and SDO), and a serial clock output (SCO).

Data is shifted in or out of the device synchronous with SCO.

The FSI and FSO signals are used to indicate to either the

device or the processor, the beginning of a word transmission

into or out of the device. The AD7725 provides the clock for

conversion and data transfers. The CFMT pin selects the active

edge of SCO during conversions and the EFMT pin selects the

active edge of SCO during configuration.

Programming the postprocessor and operating the AD7725 in

serial mode is purely pin-driven. Serial mode has three different

submodes that determine the way in which the postprocessor is to

be configured following power-up. These modes are selected by

setting the logic values on the SMODE0 and SMODE1 pins (see

Table IV). These modes are

•

DSP: The filter can be user defined and can be loaded from

a DSP.

•

EPROM: The filter can be user defined and can be loaded

from an external EPROM.

•

Boot from ROM (BFR): The default filter (stored in inter-

nal ROM) can be loaded into the postprocessor, which

allows the user to evaluate the device without having to load

configuration data.

In serial mode, several AD7725s can be daisy-chained together

so they can all be configured from one EPROM or DSP and

conversion data from all devices can be read back by one DSP.

DSP Mode–Loading Configuration Data from a DSP

In this mode, a user-defined filter can be developed and the

resulting configuration file loaded into the postprocessor from a

DSP. The DSP therefore loads data into the AD7725 and reads

back the conversion results. This mode of operation is selected by

tying SMODE0 to DVDD and SMODE1 to DGND. The values

on these pins inform the AD7725 that user-defined filter data is

to be loaded into the postprocessor from the DSP automatically

following power-up. The data is loaded using FSI and SDI and

the transfer of data is controlled by SCO. During the download

of configuration data, SCO = fCLKIN/16. Following power-on

reset, the

SOE pin goes high to inform the DSP that configura-

tion of the postprocessor can begin. If no errors occur during the

configuration, the CFGEND output will go high. In Figure 26,

the CFGEND is tied to INIT, thus it will drive INIT high, and the

part will begin converting. However, if an error does occur during

the configuration, the

ERR bit will go low, and CFGEND will not

go high. The INIT pin will therefore not start conversions. The

part will not do anything until

RESETCFG is pulsed low. When

this occurs, the part is reset,

SOE goes high, and the configuration

file is reloaded.

The AD7725 will read the entire configuration file, and, if an

error does occur during configuration, the user will be notified

only once the whole file has been read. In this case, the data will

not be loaded into the postprocessor. After data has been down-

loaded, the serial clock frequency (SCO) is selected by the value

on SCR and can be CLKIN (SCR = 0) or CLKIN/2 (SCR = 1).

SCO must have a frequency equal to CLKIN if the AD7725

outputs data at CLKIN/16. For lower output word rates, either

clock frequency can be used. To load configuration data into

the AD7725, an FSI pulse one CLKIN cycle wide informs the

AD7725 that data is being transferred into the device. The data

is loaded using the next 16 SCLK cycles following the detection

of the FSI pulse. Figure 26 shows the connection diagram for

the AD7725 when loading configuration data from a DSP, and

Figure 27 shows a flow chart of the power-up and configura-

tion sequence.

DVDD

SOE

ERR

DVAL

INIT

RESETCFG

CFGEND

SMODE1

SYNC

SCO

FSO

SDO

SDI

FSI

AD7725

SCLK0

RFS0

DR0

DT0

TFS0

ADSP-21xx

SMODE0

INT

DVDD

Figure 26. Connection Diagram for Loading the

Filter Configuration Data from a DSP

POWER-ON RESET

IMMEDIATE BOOT

FROM A DSP

USER-DEFINED FILTER

DATA LOADED INTO

THE POSTPROCESSOR

FROM A DSP

CFGEND = 1

INIT = 1

DEVICE STARTS

CONVERTING

SMODE0 = 1

SMODE1 = 0

DATA

LOADED

CORRECTLY?

PULSE

RESETCFG

LOW

YES

ERR = 0

SOE GOES HIGH

Figure 27. Flow Chart of DSP Mode

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