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Core Logic Module (Continued)

Parallel/Serial Access Trap SMI Status. Indicates whether or not an SMI was caused by a trapped I/O access to either the

serial or parallel ports.

0: No.

1: Yes.

To enable SMI generation, set F0 Index 82h[2] to 1.

Floppy Disk Access Trap SMI Status. Indicates whether or not an SMI was caused by a trapped I/O access to the floppy

disk.

0: No.

1: Yes.

To enable SMI generation, set F0 Index 82h[1] to 1.

Primary Hard Disk Access Trap SMI Status. Indicates whether or not an SMI was caused by a trapped I/O access to the

primary hard disk.

0: No.

1: Yes.

To enable SMI generation, set F0 Index 82h[0] to 1.

Index 87h

Second Level PME/SMI Status Mirror Register 4 (RO)

Reset Value: 00h

The bits in this register contain second level status reporting. Top level status is reported at F1BAR0+I/O Offset 00h/02h[0].

This register is called a “Mirror” register since an identical register exists at F0 Index F7h. Reading this register does not clear the status,

while reading its counterpart at F0 Index F7h clears the status at both the second and top levels except for bit 7 which has a third level of

SMI status reporting at F0BAR0+I/O 0Ch/1Ch.

GPIO Event SMI Status. Indicates whether or not an SMI was caused by a transition of any of the GPIOs (GPIO47-GPIO32

and GPIO15-GPIO0).

0: No.

1: Yes.

To enable SMI generation, set F1BAR1+I/O Offset 0Ch[0] to 0.

F0BAR0+I/O Offset 08h/18h selects which GPIOs are enabled to generate a PME and setting F1BAR1+I/O Offset 0Ch[0] =

0 enables the PME to generate an SMI. In addition, the selected GPIO must be enabled as an input (F0BAR0+I/O Offset

20h and 24h).

The next level (third level) of SMI status is at F0BAR0+I/O 0Ch/1Ch[15:0].

Thermal Override SMI Status. Indicates whether or not an SMI was caused by the assertion of THRM#.

0: No.

1: Yes.

To enable SMI generation, set F0 Index 83h[4] to 1.

5:4

Reserved. Always reads 0.

SIO PWUREQ SMI Status. Indicates whether or not an SMI was caused by a power-up event from the SIO.

0: No.

1: Yes.

A power-up event is defined as any of the following events/activities:

—RI2#

—SDATA_IN2

— IRRX1 (CEIR)

To enable SMI generation, set F1BAR1+I/O Offset 0Ch[0] to 0.

Codec SDATA_IN SMI Status. Indicates whether or not an SMI was caused by AC97 Codec producing a positive edge on

SDATA_IN.

0: No.

1: Yes.

To enable SMI generation, set F0 Index 80h[5] to 1.

RTC Alarm (IRQ8#) SMI Status. Indicates whether or not an SMI was caused by an RTC interrupt.

0: No.

1: Yes.

This SMI event can only occur while in 3V Suspend and an RTC interrupt occurs with F1BAR1+I/O Offset 0Ch[0] = 0.

Table 5-29. F0: PCI Header and Bridge Configuration Registers for GPIO and LPC Support (Continued)

Bit

Description

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