SC2200 datasheet(214/433 Pages) NSC

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Revision 3.0

Core Logic Module (Continued)

Primary Hard Disk Access Trap.

0: Disable.

1: Enable.

If this bit is enabled and an access occurs in the address ranges selected in F0 Index 93h[5], an SMI is generated.

Top level SMI status is reported at F1BAR0+I/O Offset 00h/02h[0].

Second level SMI status is reported at F0 Index 86h/F6h[0].

Index 83h

Power Management Enable Register 4 (R/W)

Reset Value: 00h

Secondary Hard Disk Idle Timer Enable. Turn on Secondary Hard Disk Idle Timer Count Register (F0 Index ACh) and

generate an SMI when the timer expires.

0: Disable.

1: Enable.

If an access occurs in the address ranges selected in F0 Index 93h[4], the timer is reloaded with the programmed count.

Top level SMI status is reported at F1BAR0+I/O Offset 00h/02h[0].

Second level SMI status is reported at F0 Index 86h/F6h[4].

Secondary Hard Disk Access Trap. If this bit is enabled and an access occurs in the address ranges selected in F0 Index

93h[4], an SMI is generated.

0: Disable.

1: Enable.

Top level SMI status is reported at F1BAR0+I/O Offset 00h/02h[0].

Second level SMI status is reported at F0 Index 86h/F6h[5].

ACPI Timer SMI. Allow SMI generation for MSB toggles on the ACPI Timer (F1BAR0+I/O Offset 1Ch or

F1BAR1+I/O Offset 1Ch).

0: Disable.

1: Enable.

Top level SMI status is reported at F1BAR0+I/O Offset 00h/02h[0].

Second level SMI status is reported at F0 Index 87h/F7h[0].

THRM# SMI. Allow SMI generation on assertion of THRM#.

0: Disable.

1: Enable.

Top level SMI status is reported at F1BAR0+I/O Offset 00h/02h[0].

Second level SMI status is reported at F0 Index 87h/F7h[6].

VGA Timer Enable. Turn on VGA Timer Count Register (F0 Index 8Eh) and generate an SMI when the timer reaches 0.

0: Disable.

1: Enable.

If an access occurs in the programmed address range, the timer is reloaded with the programmed count. F0 Index 8Bh[6]

selects the timebase for the VGA Timer.

SMI status is reported at F1BAR0+I/O Offset 00h/02h[6] (top level only).

Video Retrace Interrupt SMI. Allow SMI generation whenever video retrace occurs.

0: Disable.

1: Enable.

This information is decoded from the serial connection (PSERIAL register, bit 7) from the GX1 module. This function is nor-

mally not used for power management but for soft (VSA) VGA routines.

SMI status reporting is at F1BAR0+I/O Offset 00h/02h[5] (top level only).

General Purpose Timer 2 Enable. Turn on GP Timer 2 Count Register (F0 Index 8Ah) and generate an SMI when the timer

expires.

0: Disable.

1: Enable.

This idle timer is reloaded from the assertion of GPIO7 (if programmed to do so). GP Timer 2 programming is at F0 Index

8Bh[5,3,2].

Top level SMI status is reported at F1BAR0+I/O Offset 00h/02h[9].

Second level SMI status is reported at F1BAR0+I/O Offset 04h/06h[1].

Table 5-29. F0: PCI Header and Bridge Configuration Registers for GPIO and LPC Support (Continued)

Bit

Description

SC2200 Datasheet(PDF) 214 Page - National Semiconductor (TI)

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