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Core Logic Module (Continued)

User Defined Device 1 (UDEF1) Idle Timer Enable. Turn on UDEF1 Idle Timer Count Register (F0 Index A0h) and gener-

ate an SMI when the timer expires.

0: Disable.

1: Enable.

If an access occurs in the programmed address range, the timer is reloaded with the programmed count.

UDEF1 address programming is at F0 Index C0h (base address register) and CCh (control register).

Top level SMI status is reported at F1BAR0+I/O Offset 00h/02h[0].

Second level SMI status is reported at F0 Index 85h/F5h[4].

Keyboard/Mouse Idle Timer Enable. Turn on Keyboard/Mouse Idle Timer Count Register (F0 Index 9Eh) and generate an

SMI when the timer expires.

0: Disable.

1: Enable.

If an access occurs in the address ranges listed below, the timer is reloaded with the programmed count:

— Keyboard Controller: I/O Ports 060h/064h.

— COM1: I/O Port 3F8h-3FFh (if F0 Index 93h[1:0] = 10 this range is included).

— COM2: I/O Port 2F8h-2FFh (if F0 Index 93h[1:0] = 11 this range is included).

Top level SMI status is reported at F1BAR0+I/O Offset 00h/02h[0].

Second level SMI status is reported at F0 Index 85h/F5h[3].

Parallel/Serial Idle Timer Enable. Turn on Parallel/Serial Port Idle Timer Count Register (F0 Index 9Ch) and generate an

SMI when the timer expires.

0: Disable.

1: Enable.

If an access occurs in the address ranges listed below, the timer is reloaded with the programmed count.

— LPT1: I/O Port 3BCh-3BEh.

— LPT2: I/O Port 378h-37Fh.

— COM1: I/O Port 3F8h-3FFh (if F0 Index 93h[1:0] = 10 this range is excluded).

— COM2: I/O Port 2F8h-2FFh (if F0 Index 93h[1:0] = 11 this range is excluded).

— COM3: I/O Port 3E8h-3EFh.

— COM4: I/O Port 2E8h-2EFh.

Top level SMI status is reported at F1BAR0+I/O Offset 00h/02h[0].

Second level SMI status is reported at F0 Index 85h/F5h[2].

Floppy Disk Idle Timer Enable. Turn on Floppy Disk Idle Timer Count Register (F0 Index 9Ah) and generate an SMI when

the timer expires.

0: Disable.

1: Enable.

If an access occurs in the address ranges (listed below, the timer is reloaded with the programmed count.

— Primary floppy disk: I/O Port 3F2h-3F5h, 3F7h.

— Secondary floppy disk: I/O Port 372h-375h, 377h.

Top level SMI status is reported at F1BAR0+I/O Offset 00h/02h[0].

Second level SMI status is reported at F0 Index 85h/F5h[1].

Primary Hard Disk Idle Timer Enable. Turn on Primary Hard Disk Idle Timer Count Register (F0 Index 98h) and generate

an SMI when the timer expires.

0: Disable.

1: Enable.

If an access occurs in the address ranges selected in F0 Index 93h[5], the timer is reloaded with the programmed count.

Top level SMI status is reported at F1BAR0+I/O Offset 00h/02h[0].

Second level SMI status is reported at F0 Index 85h/F5h[0].

Index 82h

Power Management Enable Register 3 (R/W)

Reset Value: 00h

Video Access Trap. If this bit is enabled and an access occurs in the video address range (sets bit 0 of the GX1 module’s

PSERIAL register), an SMI is generated.

0: Disable.

1: Enable.

Top level SMI status is reported at F1BAR0+I/O Offset 00h/02h[0].

Second level SMI status is reported at F0 Index 86h/F6h[7].

Table 5-29. F0: PCI Header and Bridge Configuration Registers for GPIO and LPC Support (Continued)

Bit

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