SC2200 datasheet(271/433 Pages) NSC

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Core Logic Module (Continued)

Audio Bus Master 2 SMI Status. Indicates if an SMI was caused by an event occurring on Audio Bus Master 2.

0: No.

1: Yes.

SMI generation is enabled when Audio Bus Master 2 is enabled (F3BAR0+Memory Offset 30h[0] = 1).

An SMI is then generated when the End of Page bit is set in the Audio Bus Master 2 SMI Status Register (F3BAR0+Memory

Offset 31h[0] = 1).

Audio Bus Master 1 SMI Status. Indicates if an SMI was caused by an event occurring on Audio Bus Master 1.

0: No.

1: Yes.

SMI generation is enabled when Audio Bus Master 1 is enabled (F3BAR0+Memory Offset 28h[0] = 1).

An SMI is then generated when the End of Page bit is set in the Audio Bus Master 1 SMI Status Register (F3BAR0+Memory

Offset 29h[0] = 1).

Audio Bus Master 0 SMI Status. Indicates if an SMI was caused by an event occurring on Audio Bus Master 0.

0: No.

1: Yes.

SMI generation is enabled when Audio Bus Master 0 is enabled (F3BAR0+Memory Offset 20h[0] = 1).

An SMI is then generated when the End of Page bit is set in the Audio Bus Master 0 SMI Status Register (F3BAR0+Memory

Offset 21h[0] = 1).

Codec Serial or GPIO Interrupt SMI Status. Indicates if an SMI was caused by a serial or GPIO interrupt from codec.

0: No.

1: Yes.

SMI generation enabling for codec serial interrupt: F3BAR0+Memory Offset 08h[23] = 1.

SMI generation enabling for codec GPIO interrupt: F3BAR0+Memory Offset 00h[30] = 1.

I/O Trap SMI Status. Indicates if an SMI was caused by an I/O trap.

0: No.

1: Yes.

The next level (third level) of SMI status reporting is at F3BAR0+Memory Offset 14h.

Offset 12h-13h

Second Level Audio SMI Status Mirror Register (RO)

Reset Value: 0000h

Note:

The bits in this register contain second level SMI status reporting. Top level is reported at F1BAR0+I/O Offset 00h/02h[1].

Reading this register does not clear the status bits. See F3BAR0+Memory Offset 10h.

15:8

Reserved. Must be set to 0.

Audio Bus Master 5 SMI Status. Indicates if an SMI was caused by an event occurring on Audio Bus Master 5.

0: No.

1: Yes.

SMI generation is enabled when Audio Bus Master 5 is enabled (F3BAR0+Memory Offset 48h[0] = 1). An SMI is then gen-

erated when the End of Page bit is set in the SMI Status Register (F3BAR0+Memory Offset 49h[0] = 1). The End of Page bit

must be cleared before this bit can be cleared.

Audio Bus Master 4 SMI Status. Indicates if an SMI was caused by an event occurring on Audio Bus Master 4.

0: No.

1: Yes.

SMI generation is enabled when Audio Bus Master 4 is enabled (F3BAR0+Memory Offset 40h[0] = 1). An SMI is then gen-

erated when the End of Page bit is set in the SMI Status Register (F3BAR0+Memory Offset 41h[0] = 1). The End of Page bit

must be cleared before this bit can be cleared.

Audio Bus Master 3 SMI Status. Indicates if an SMI was caused by an event occurring on Audio Bus Master 3.

0: No.

1: Yes.

SMI generation is enabled when Audio Bus Master 3 is enabled (F3BAR0+Memory Offset 38h[0] = 1). An SMI is then gen-

erated when the End of Page bit is set in the SMI Status Register (F3BAR0+Memory Offset 39h[0] = 1). The End of Page bit

must be cleared before this bit can be cleared.

Table 5-38. F3BAR0+Memory Offset: XpressAUDIO Configuration Registers (Continued)

Bit

Description

SC2200 Datasheet(PDF) 271 Page - National Semiconductor (TI)

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