SC2200 datasheet(276/433 Pages) NSC

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Revision 3.0

Core Logic Module (Continued)

Assert Masked Internal IRQ15.

0: Disable.

1: Enable.

Assert Masked Internal IRQ14.

0: Disable.

1: Enable.

Reserved. Set to 0.

Assert Masked Internal IRQ12.

0: Disable.

1: Enable.

Assert masked internal IRQ11.

0: Disable.

1: Enable.

Assert Masked Internal IRQ10.

0: Disable.

1: Enable.

Assert Masked Internal IRQ9.

0: Disable.

1: Enable.

Reserved. Set to 0.

Assert Masked Internal IRQ7.

0: Disable.

1: Enable.

Reserved. Set to 0.

Assert Masked Internal IRQ5.

0: Disable.

1: Enable.

Assert Masked Internal IRQ4.

0: Disable.

1: Enable.

Assert Masked Internal IRQ3.

0: Disable.

1: Enable.

2:0

Reserved. Must be set to 0.

Offset 20h

Audio Bus Master 0 Command Register (R/W)

Reset Value: 00h

Audio Bus Master 0: Output to codec; 32-bit; Left and Right Channels; Slots 3 and 4.

7:4

Reserved. Must be set to 0. Must return 0 on reads.

Read or Write Control. Sets the transfer direction of the Audio Bus Master.

0: PCI reads are performed.

1: PCI writes are performed.

This bit must be set to 0 (read), and should not be changed when the bus master is active.

2:1

Reserved. Must be set to 0. Must return 0 on reads.

Bus Master Control. Controls the state of the Audio Bus Master.

0: Disable.

1: Enable.

Setting this bit to 1 enables the bus master to begin data transfers.

When writing 0 to this bit, the bus master must either be paused, or reach EOT. Writing 0 to this bit while the bus master is

operating may result in unpredictable behavior (and may crash the bus master state machine). The only recovery from such

unpredictable behavior is a PCI reset.

Table 5-38. F3BAR0+Memory Offset: XpressAUDIO Configuration Registers (Continued)

Bit

Description

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