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278

Revision 3.0

Core Logic Module (Continued)

Offset 29h

Audio Bus Master 1 SMI Status Register (RC)

Reset Value: 00h

Audio Bus Master 1: Input from codec; 32-Bit; Left and Right Channels; Slots 3 and 4.

7:2

Reserved.

Bus Master Error. Indicates if hardware encountered a second EOP before software has cleared the first.

0: No.

1: Yes.

If hardware encounters a second EOP (end of page) before software has cleared the first, it causes the bus master to pause

until this register is read to clear the error.

End of Page. Indicates if the bus master transferred data which is marked by EOP bit in the PRD table (bit 30).

0: No.

1: Yes.

Offset 2Ah-2Bh

Not Used

Offset 2Ch-2Fh

Audio Bus Master 1 PRD Table Address (R/W)

Reset Value: 00000000h

Audio Bus Master 1: Input from codec; 32-Bit; Left and Right Channels; Slots 3 and 4.

31:2

Pointer to the Physical Region Descriptor Table. This bit field is a PRD table pointer for Audio Bus Master 1.

When written, this register points to the first entry in a PRD table. Once Audio Bus Master 1 is enabled (Command Register

bit 0 = 1), it loads the pointer and updates this register (by adding 08h) so that it points to the next PRD.

When read, this register points to the next PRD.

1:0

Reserved. Must be set to 0.

Note:

The Physical Region Descriptor (PRD) table consists of one or more entries - each describing a memory region to or from

which data is to be transferred. Each entry consists of two DWORDs.

DWORD 0:

[31:0]

= Memory Region Physical Base Address

DWORD 1:

= End of Table Flag

= End of Page Flag

= Loop Flag (JMP)

[28:16]

= Reserved (0)

[15:0]

= Byte Count of the Region (Size)

Offset 30h

Audio Bus Master 2 Command Register (R/W)

Reset Value: 00h

Audio Bus Master 2: Output to codec; 16-Bit; Slot 5.

7:4

Reserved. Must be set to 0. Must return 0 on reads.

Read or Write Control. Sets the transfer direction of Audio Bus Master 2.

0: PCI reads are performed.

1: PCI writes are performed.

This bit must be set to 0 (read) and should not be changed when the bus master is active.

2:1

Reserved. Must be set to 0. Must return 0 on reads.

Bus Master Control. Controls the state of the Audio Bus Master 2.

0: Disable.

1: Enable.

Setting this bit to 1 enables the bus master to begin data transfers. When writing 0 to this bit, the bus master must be either

paused or reached EOT. Writing 0 to this bit while the bus master is operating results in unpredictable behavior (and may

crash the bus master state machine). The only recovery from this condition is a PCI reset.

Table 5-38. F3BAR0+Memory Offset: XpressAUDIO Configuration Registers (Continued)

Bit

Description

SC2200 Datasheet(PDF) 278 Page - National Semiconductor (TI)

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