SC2200 datasheet(307/433 Pages) NSC

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Core Logic Module (Continued)

Table 5-45. Programmable Interval Timer Registers

Bit

Description

I/O Port 040h

Write

PIT Timer 0 Counter

7:0

Counter Value.

Read

PIT Timer 0 Status

Counter Output. State of counter output signal.

Counter Loaded. Indicates if the last count written is loaded.

0: Yes.

1: No.

5:4

Current Read/Write Mode.

00: Counter latch command.

01: R/W LSB only.

10: R/W MSB only.

11: R/W LSB, followed by MSB.

3:1

Current Counter Mode. 0-5.

BCD Mode.

0: Binary.

1: BCD (Binary Coded Decimal).

I/O Port 041h

Write

PIT Timer 1 Counter (Refresh)

7:0

Counter Value.

Read

PIT Timer 1 Status (Refresh)

Counter Output. State of counter output signal.

Counter Loaded. Indicates if the last count written is loaded.

0: Yes.

1: No.

5:4

Current Read/Write Mode.

00: Counter latch command.

01: R/W LSB only.

10: R/W MSB only.

11: R/W LSB, followed by MSB.

3:1

Current Counter Mode. 0-5.

BCD Mode.

0: Binary.

1: BCD (Binary Coded Decimal).

SC2200 Datasheet(PDF) 307 Page - National Semiconductor (TI)

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