SC2200 datasheet(314/433 Pages) NSC

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Core Logic Module (Continued)

IRQ3 Edge or Level Sensitive Select. Selects PIC IRQ3 sensitivity configuration.

0: Edge.

1: Level.

2:0

Reserved. Must be set to 0.

I/O Port 4D1h

Interrupt Edge/Level Select Register 2 (R/W)

Reset Value: 00h

Notes:

If ICW1 - bit 3 in the PIC is set as level, it overrides the setting for bits 7:6 and 4:1 in this register.

Bits [7:6] and [4:1] in this register are used to configure a PCI interrupt mapped to IRQ[x] on the PIC as level-sensitive

(shared).

IRQ15 Edge or Level Sensitive Select. Selects PIC IRQ15 sensitivity configuration.

0: Edge.

1: Level.

IRQ14 Edge or Level Sensitive Select. Selects PIC IRQ14 sensitivity configuration.

0: Edge.

1: Level.

Reserved. Must be set to 0.

IRQ12 Edge or Level Sensitive Select. Selects PIC IRQ12 sensitivity configuration.

0: Edge.

1: Level.

IRQ11 Edge or Level Sensitive Select. Selects PIC IRQ11 sensitivity configuration.

0: Edge.

1: Level.

IRQ10 Edge or Level Sensitive Select. Selects PIC IRQ10 sensitivity configuration.

0: Edge.

1: Level.

IRQ9 Edge or Level Sensitive Select. Selects PIC IRQ9 sensitivity configuration.

0: Edge.

1: Level.

Reserved. Must be set to 0.

Table 5-49. Miscellaneous Registers (Continued)

Bit

Description

SC2200 Datasheet(PDF) 314 Page - National Semiconductor (TI)