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ST7LITEUS5 Datasheet(PDF) 75 Page - STMicroelectronics |
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ST7LITEUS5 Datasheet(HTML) 75 Page - STMicroelectronics |
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75 / 136 page  Obsolete Product(s) - Obsolete Product(s) Obsolete Product(s) - Obsolete Product(s) ST7LITEUS2, ST7LITEUS5 On-chip peripherals 75/136 Counter register high (CNTRH) Reset value: 0000 0000 (00h) Counter register low (CNTRL) This 12-bit register is read by software and cleared by hardware after a reset. The counter is incremented continuously as soon as a counter clock is selected. To obtain the 12-bit value, software should read the counter value in two consecutive read operations. As there is no latch, it is recommended to read LSB first. In this case, CNTRH can be incremented between the two read operations and to have an accurate result when ftimer = fCPU, special care must be taken when CNTRL values close to FFh are read. When a counter overflow occurs, the counter restarts from the value specified in the ATR register. Reset value: 0000 0000 (00h) Auto reload register (ATRH) Reset value: 0000 0000 (00h) Table 29. Counter clock selection Counter clock selection CK1 CK0 OFF 0 0 fLTIMER (1 ms timebase @ 8 MHz) 0 1 fCPU 10 Reserved 1 1 15 8 0 0 0 0 CN11 CN10 CN9 CN8 Read only 7 0 CN7 CN6 CN5 CN4 CN3 CN2 CN1 CN0 Read only Bits 15:12 Reserved, must be kept cleared. Bits 11:0 CNTR[11:0] Counter value. 15 8 0 0 0 0 ATR11 ATR10 ATR9 ATR8 Read/Write Obsolete Product(s) - Obsolete Product(s) |
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