ST7LITEUS5 datasheet(47/136 Pages) STMICROELECTRONICS

47 / 136 page

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Interrupts

47/136

AVD Threshold Selection register (AVDTHCR)

Refer to Section 6.3.4: AVD Threshold Selection register (AVDTHCR) for a full description of

this register.

Application notes

The LVDRF flag is not cleared when another reset type occurs (external or watchdog), the

LVDRF flag remains set to keep trace of the original failure.

In this case, a watchdog reset can be detected by software while an external reset can not.

Bit 2 LVDRF LVD reset flag

This bit indicates that the last Reset was generated by the LVD block. It is set by

hardware (LVD reset) and cleared when read. See WDGRF flag description in

Section 10.1.6 on page 69 for more details. When the LVD is disabled by OPTION

BYTE, the LVDRF bit value is undefined.

Note: If the selected clock source is one of the two internal ones, and if VDD

remains below the selected LVD threshold during less than TAWU (33us

typ.), the LVDRF flag cannot be set even if the device is reset by the LVD.

If the selected clock source is the external clock (CLKIN), the flag is never

set if the reset occurs during Halt mode. In run mode the flag is set only if

fCLKIN is greater than 10 MHz.

Bit 1 AVDF Voltage Detector flag

This read-only bit is set and cleared by hardware. If the AVDIE bit is set, an

interrupt request is generated when the AVDF bit is set. Refer to Figure 17 for

additional details

0: VDD over AVD threshold

1: VDD under AVD threshold

Bit 0 AVDIE Voltage Detector interrupt enable

This bit is set and cleared by software. It enables an interrupt to be generated when

the AVDF flag is set. The pending interrupt information is automatically cleared

when software enters the AVD interrupt routine.

0: AVD interrupt disabled

1: AVD interrupt enabled

Table 13.

System integrity register map and reset values

Address

(Hex.)

label

765432

003Ah

SICSR

reset

value

01100

LVDRF

AVDF

AVDIE

003Eh

AVDTHCR

reset

value

CK2

CK1

CK0

000

AVD1

AVD2

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