ST7LITEUS5 datasheet(30/136 Pages) STMICROELECTRONICS

30 / 136 page

Obsolete

Product(s)

- Obsolete

Product(s)

Obsolete

Product(s)

- Obsolete

Product(s)

Supply, reset and clock management

ST7LITEUS2, ST7LITEUS5

30/136

Figure 9.

Clock switching

6.3

6.3.1

Main Clock Control/Status register (MCCSR)

Reset value: 0000 0000 (00h)

Internal RC

AWU RC

Set RC/AWU

Poll AWU_FLAG until set

Internal RC

Reset RC/AWU

Poll RC_FLAG until set

AWU RC

000

MCO

SMS

Read / Write

Bits 7:2 Reserved, must be kept cleared.

Bit 1 MCO Main Clock Out enable bit

This bit is read/write by software and cleared by hardware after a reset. This bit

allows to enable the MCO output clock.

0: MCO clock disabled, I/O port free for general purpose I/O.

1: MCO clock enabled.

Bit 0 SMS Slow Mode select

This bit is read/write by software and cleared by hardware after a reset. This bit

selects the input clock fOSC or fOSC/32.

0: Normal mode (fCPU = fOSC )

1: Slow mode (fCPU = fOSC/32)

Obsolete

Product(s)

- Obsolete

Product(s)

ST7LITEUS5 Datasheet(PDF) 30 Page - STMicroelectronics

ST7LITEUS5 Datasheet(HTML) 30 Page - STMicroelectronics

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL