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ST7LITEUS5 Datasheet(PDF) 17 Page - STMicroelectronics |
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ST7LITEUS5 Datasheet(HTML) 17 Page - STMicroelectronics |
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17 / 136 page  Obsolete Product(s) - Obsolete Product(s) Obsolete Product(s) - Obsolete Product(s) ST7LITEUS2, ST7LITEUS5 Register and memory map 17/136 0049h 004Ah AWU AWUPR AWUCSR AWU Prescaler register AWU Control/Status register FFh 00h R/W R/W 004Bh 004Ch 004Dh 004Eh 004Fh 0050h DM(4) DMCR DMSR DMBK1H DMBK1L DMBK2H DMBK2L DM Control register DM Status register DM Breakpoint register 1 High DM Breakpoint register 1 Low DM Breakpoint register 2 High DM Breakpoint register 2 Low 00h 00h 00h 00h 00h 00h R/W R/W R/W R/W R/W R/W 0051h to 007Fh Reserved area (47 bytes) 1. Legend: x=undefined, R/W=read/write 2. The contents of the I/O port DR registers are readable only in output configuration. In input configuration, the values of the I/O pins are returned instead of the DR register contents. 3. The bits associated with unavailable pins must always keep their reset value. 4. For a description of the DM registers, see the ST7 I2C Protocol Reference Manual. Table 3. Hardware register map (continued)(1) Address Block Register label Register name Reset status Remarks Obsolete Product(s) - Obsolete Product(s) |
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