Pin Descriptions

Symbol

DP8473

DP8473

Function

PCC

DIP

A0 A1 A2

19 – 21

17 – 19

Address lines from the microprocessor This determines which registers the

microprocessor is accessing as shown in Table IV in the Register Description Section

Don’t care during DMA transfers

CS

18

16

Active low input to enable the RD and WR inputs Not required during DMA transfers

This should be held high during DMA transfers

DAK

32

30

Active low input to acknowledge the DMA request and enable the RD and WR inputs

This signal is enabled when D3 of the Drive Control Register is set

DIR

4

2

out) When in the write or read modes this output will be high This is a high drive open

drain output

DRQ

31

29

Active high output to signal the DMA controller that a data transfer is needed This signal

is enabled when D3 of the Drive Control Register is set

DRV TYP

47

43

This is an input used by the controller to enable the 300 kbs mode This enables the use

of floppy drives with either dual or single speed spindle motors For dual speed spindle

motors this pin is tied low When low and 300 kbs data rate is selected in the data rate

register the PLL actually uses 250 kbs This pin is tied high for single speed spindle

motor drives (standard AT drive) When this pin is high and 300 kbs is selected 300 kbs

is used (See also RPMLC pin)

DR0

6

4

This is an active low drive select line for drive 0 that is controlled by the Drive Control

register bits D0 D1 The Drive Select bit is ANDed with the Motor Enable of the same

number This is a high drive open drain output

DR1

5

3

This is an active low drive select similar to DR0 line except for drive 1

DR2

45

This is the same as DR0 except for drive 2

DR3

43

This is the same as DR0 except for drive 3

DSKCHGRG

35

33

This latched Schmitt input signal is inverted and routed to D7 of the data bus and is read

when address xx7H is enabled DSKCHG is a disk drive output that indicates when the

drive door has been opened When the RG bit in the Mode Command is set this pin

functions as a Read Gate signal that when low forces the data separator to lock to the

crystal and when high it locks to data for diagnostic purposes

D0 – D4

22-26

20 – 24

Bi-directional data lines to the microprocessor These are the lower 5 bits and have

buffered 12 mA outputs

D5 – D7

28 – 30

26 – 28

Bi-directional data lines to the microprocessor These upper 3 bits have buffered 12 mA

outputs

FGND250

42

40

This pin connects the PLL filter for 250k(MFM)125k(FM) bs or 300k(MFM)150k(FM)

bs to ground This is a low impedance open drain output

FGND500

41

39

This pin connects the PLL filter for 500k(MFM)250k(FM) bs to ground This is a low

impedance open drain output

FILTER

40

38

This pin is the output of the charge pump and the input to the VCO One or more filters

are attached between this pin and the GNDA FGND250 and FGND500 pins

GNDA

39

37

This pin is the analog ground for the data separator including all primary and secondary

PLLs and delay lines

GNDB

27

25

This pin is the digital ground for the 12 mA microprocessor interface buffers This

includes D0 – D7 INT and DRQ

GNDC

36

34

This pin is the digital ground for the controller’s digital logic including all internal registers

micro-engine etc

GNDD

2

48

This pin is the digital ground for the disk interface output drivers

HD SEL

9

7

Head 0 This is a high drive open drain output

INDEX

11

9

This active low Schmitt input signals the beginning of a track

INT

34

32

Active high output to signal that an operation requires the attention of the

microprocessor The action required depends on the current function of the controller

This signal is enabled when D3 of the Drive Control Register is set

3