TLF9384 – 5

FIGURE 3 Block Diagram of DP8473’s Data Separator

TLF9384 – 6

TLF9384 – 7

TLF9384 – 8

a) Single Data Rate

b) 250500 kbs Filter

c) 250500 kbs and 1 Mbs

Note

For all filter configurations 250kbs and 300 kbs share the same filter

FIGURE 4 Typical Configuration for Loop Filters for the DP8473 Showing Component Labels

To ensure optimal performance the data separator incorpo-

rates several additional circuits The quarter period delay

line is used to determine the center of each bit cell A sec-

ondary PLL is used to automatically calibrate the quarter

period delay line The secondary PLL also calibrates the

center frequency of the VCO

To eliminate the logic associated with controlling multiple

data rates the DP8473 supports the connection of three

filters to the chip via the FGND250 and FGND500 pins (fil-

ter ground switches) The controller chooses which filter

components to use based on the value loaded in the Data

Rate Register If 500 k(MFM) is being used then the

FGND500 is enabled (FGND250 is disabled) If 250 k(MFM)

or 300 k(MFM) is being used the FGND250 pin is enabled

and FGND500 is disabled For 1 Mbs (MFM) both FGND

pins are disabled

Note for FM encoding

Sometimes after a reset the DP8473 will consist-

ently return an error in the Result Phase after an FM read command If this

occurs simply reset the DP8473 and retry the operation This may have to

be done more than once as many as five times Resetting and repeating will

prevent soft errors being reported prematurely This technique is used by

MS-DOS

Figure 4 shows several possible filter configurations For a

filter to cover all data rates (

Figure 4c ) the DP8473 has a 1

Mbs filter always connected and other capacitor filter com-

ponents for the other data rates are switched in parallel to

this filter The actual loop filter for 500 kbs is the parallel

to the FGND500 pin and to ground The 250300 kbs filter

attached to the FGND250 and ground If 1 Mbs need not

be supported then the filter configuration of

Figure 4b can

be used This configuration allows more optimal perform-

ance for both 500k and 250300 kbs

Figure 4a is a simple

filter configuration primarily for a single data rate (or multiple

data rates with a performance compromise) Table II shows

some typical filter values Other filter configurations and val-

ues are possible these result in good general performance

While the controller and data separator support both FM

and MFM encoding the filter switch circuitry only supports

6