DP8473 datasheet(10/28 Pages) NSC

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TABLE VI Data Rate and Precompensation Programming Values

DRVTYP

Data Rate

Normal

Alternate

FGND

RPMLC

MFM

Precomp

(kbs)

(ns)

Enabled

Level

500

125

FGND500

High

250

125

250

FGND250

Low

300

208

FGND250

Low

250

125

250

FGND250

Low

250

125

250

FGND250

Low

1000

None

High

1000

None

Low

Normal values when PUMPPREN pin set low Alternate values when PUMPPREN pin set high

D0 and D1 are Data Rate Control Bits

DRIVE CONTROL REGISTER (Write Only)

D7 Motor Enable 3

This controls the Motor for drive 3

MTR3 When 0 the output is high when 1 the output is low

(Note this signal is not output to a pin on 48 pin DIP ver-

sion)

D6 Motor Enable 2

Same function as D7 except for drive

2’s motor (Note this signal is not brought out to a pin on

DIP)

D5 Motor Enable 1

This bit controls the Motor for drive 1’s

motor When this bit is 0 the MTR1 output is high

D4 Motor Enable 0

Same as D5 except for drive 0’s motor

D3 DMA Enable

When set to a 1 this enables the DRQ

DAK INT pins A zero disables these signals

D2 Reset Controller

This bit when set to a 0 resets the

controller and when a 1 enables normal operation It does

not affect the Drive Control or Data Rate Registers which

are reset only by a hardware reset

D1 – D0 Drive Select

These two pins are encoded for the

four drive selects and are gated with the motor enable

lines so that only one drive is selected when it’s Motor En-

able is active (See Table V)

DATA RATE REGISTER (Write Only)

D7 – D2

Not used

D1 D0 Data Rate Select

These bits set the data rate and

the write precompensation values for the disk controller Af-

ter a hardware reset these bits are set to 10 (250 kbs)

They are encoded as shown in Table VI

DISK CHANGED REGISTER (Read Only)

D7 Disk Changed

This bit is the latched complement of the

Disk Changed input pin If the DSKCHG input is low this bit

is high

D6 – D0

These bits are reserved for use by the hard disk

controller thus during a read of this register these bits are

TRI-STATE

Result Phase Status Registers

The Result Phase of a command contains bytes that hold

status information The format of these bytes are described

below Do not confuse these register bytes with the Main

Status Register which is a read only register that is always

available The Result Phase status registers are read from

the Data Register only during the Result Phase

STATUS REGISTER 0 (ST0)

D7–D6 Interrupt Code

00 e Normal Termination of Command

01 e Abnormal Termination of Command Execu-

tion of Command was started but was not success-

fully completed

10 e Invalid Command Issue Command Issued

was not recognized as a valid command

11 e Ready changed state during the polling mode

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