DP8473 datasheet(20/28 Pages) NSC

20 / 28 page

Command Description (Continued)

SENSE DRIVE STATUS

This two byte command obtains the status of a disk drive

Status Register 3 is returned in the result phase and con-

tains the drive status This command does not generate an

interrupt

MODE

This command is used to select the special features of the

controller The bits for the command phase bytes are shown

in the command description table and their function is de-

scribed below The defaults after a hardware or software

reset are shown by the ‘‘bullets’’ to the left of each item

TMRe0 (motor TiMeR) Timers for motor on and motor

off are defined for Mode 1 (See Specify Command)

TMRe1

Timers for motor on and motor off are defined

for Mode 2 (See Specify Command)

LW PR (LoW PoweR)

00 Completely disable the low power mode (default)

01 Go into low power mode 500 ms after the head un-

load timer times out

10 Go into low power mode now

11 Not Used

IAFe0 (Index Address Format) The controller will for-

mat tracks with the Index Address Field included (IBM

Format)

IAFe1

The controller will format tracks without includ-

ing the Index Address Mark Field (ISO Format)

IPSe0 (ImPlied Seek) The implied seek bit in the com-

mand is ignored

IPSe1

The implied seek bit in the command is enabled

so that if the bit is set in the command a Seek will be

performed automatically

ETRe0 (Extended Track Range) Header format is the

IBM System 34 (double density) or System 3740 (single

density)

ETRe1

Header format is the same as above but there

are 12 bits of track number The MSB’s of the track num-

ber are in the upper four bits of the head number byte

WLDe0 (scan WiLD card) An FF(hex) from either the

P or the disk during a Scan Command is interpreted as

a wildcard character that will always match true

WLDe1

The Scan commands do not recognize FF(hex)

as a wildcard character

Head Settle

Time allowed for head to settle after an

Implied Seek Time e N c 4 ms (0 ms – 60 ms) (Based

on 500 kbs and 1 Mbs MFM data rates Double for

250 kbs)

PU (PUMP Pulse Output)

When set enables a signal

that indicates when the Data Separator’s charge pump is

making a phase correction This is a series of pulses This

signal is output on the PUMPPREN pin when this bit is

set

This is intended as a test mode to aid in evaluation of the

Data Separator (Default mode is off)

RG (Read Gate)

Like the PUMP output when this bit is

set it enables a pin (the DSKCHG pin) to act as an exter-

nal Read Gate signal for the Data Separator This is in-

tended as a test mode to aid in evaluation of the Data

Separator (Default mode is off)

SET TRACK

This command is used to inspect or change the value of the

internal Present Track Register This could be useful for re-

covery from disk mis-tracking errors where the real current

track could be read through the Read ID command and then

the Set Track Command can set the internal present track

The first byte of the command contains the command op-

code and the RW bit If the RW bit is low a track register

is to be read In this case the result phase contains the

value in the internal register specified and the third byte of

the command is a dummy byte

If the RW bit is high data is written to a track register In

this case the 3rd byte of the command phase is forced into

the specified internal register and the result phase contains

the new byte value written

The particular track register chosen to operate on is deter-

mined by the least significant 3 bits of the second byte of

the command The two LSB’s select the drive (DR1 DR0)

and the next bit (MSB) determines whether the least signifi-

cant byte (MSBe0) or the most significant byte (MSBe1)

of the track register is to be readwritten When not in the

extended track range mode only the LSB track register

need be updated In this instance the MSB bit is set to 0

This command does not generate an interrupt

INVALID COMMAND

If an invalid command (ie a command not defined) is re-

ceived by the controller the controller will respond with ST0

in the Result Phase The Controller does not generate an

interrupt during this condition Bits 6 and 7 in the Main

Status Register are both set to one’s indicating to the proc-

essor that the Controller is in the Result Phase and the

contents of ST0 must be read When the system reads ST0

it will find an 80(hex) indicating an invalid command was

received

Typical Performance Characteristics

Typical Window Margin Performance

Characteristics at 250 kbs MFM

TLF9384 – 18

Typical Window Margin Performance

Characteristics at 500 kbs MFM

TLF9384 – 19

DP8473 Datasheet(PDF) 20 Page - National Semiconductor (TI)

DP8473 Datasheet(HTML) 20 Page - National Semiconductor (TI)

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28

Datasheet Download

Link URL