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DP8473 Datasheet(PDF) 4 Page - National Semiconductor (TI) |
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DP8473 Datasheet(HTML) 4 Page - National Semiconductor (TI) |
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4 / 28 page ![]() Pin Descriptions (Continued) Symbol DP8473 DP8473 Function PCC DIP MTR0 8 6 This is an active low motor enable line for drive 0 which is controlled by the Drive Control register This is a high drive open drain output MTR1 7 5 This is an active low motor enable line for drive 1 Similar to MTR0 MTR2 1 This is an active low motor enable line for drive 2 Similar to MTR0 MTR3 52 This is an active low motor enable line for drive 3 Similar to MTR0 OSC1 38 36 One side of an external 24 MHz crystal is attached here This pin is tied low if an external clock is used OSC2CLOCK 37 35 One side of the external 24 MHz crystal is attached here If a crystal is not used a TTL or CMOS compatible clock is connected to this pin PUMPPREN 46 42 When the PU bit is set in Mode Command this pin is an output that indicates when the charge pump is making a correction Otherwise this pin is an input that sets the precomp mode as shown in Table VI If pin is configured as PUMP PREN is assumed high RD 17 15 Active low input to signal a read from the controller to the microprocessor RDATA 44 41 The active low raw data read from the disk is connected here This is a Schmitt input RESET 15 13 Active high input that resets the controller to the idle state and resets all the output lines to the disk drive to their disabled state The Drive Control register is reset to 00 The Data Rate register is set to 250 kbs The Specify command registers are not affected The Mode Command registers are set to the default values Reset should be held active during power up To prevent glitches activating the reset sequence a small capacitor (1000 pF) should be attached to this pin RPMLC 51 47 This high drive open drain output pin has two functions based on the selection of the DRVTYP pin 1 When using a dual speed spindle motor floppy drive (DRVTYP pin low) this output is used to select the spindle motor speed either 300 RPM or 360 RPM In this mode this output goes low when 250300 kbdata rate is chosen in the data rate register and high when 500 kbs is chosen 2 When using a single speed spindle motor floppy drive (DRVTYP pin high) this pin indicates when to reduce the write current to the drive This output is high for high density media (when 500 kbs is chosen) SETCUR 48 44 An external resistor connected from this pin to analog ground programs the amount of charge pump current that drives the external filters The PLL Filter Design section shows how to determine the values STEP 50 46 This active low open drain high drive output will produce a pulse at a software programmable rate to move the head during a seek operation TC 33 31 Active high input to indicate the termination of a DMA transfer This signal is enabled when the DMA Acknowledge pin is active TRK0 10 8 This active low Schmitt input tells the controller that the head is at track zero of the selected disk drive WDATA 3 1 This is the active low open drain write precompensated serial data to be written onto the selected disk drive This is a high drive open drain output WGATE 49 45 This active low open drain high drive output enables the write circuitry of the selected disk drive This output has been designed to prevent glitches during power up and power down This prevents writing to the disk when power is cycled WR 16 14 Active low input to signal a write from the microprocessor to the controller WRT PRT 12 10 This active low Schmitt input indicates that the disk is write protected Any command that writes to that disk drive is inhibited when a disk is write protected VCC 14 12 This pin is the 5V supply for the digital circuitry VCCA 13 11 This pin is the 5V supply for the analog data separator circuitry 4 |
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