DP8473 datasheet(12/28 Pages) NSC

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Result Phase Status Registers (Continued)

TABLE VIII Summary of FDC Registers

Bits

DCR (W)

MTR3

MTR2

MTR1

MTR0

DMA

Software

Drive

Enable

Reset

Select 1

Select 0

MSR (R)

Request

Data

Non-DMA

Command

Drive 3

Drive 2

Drive 1

Drive 0

for

Direction

Execution

Seeking

Master

Progress

DR (RW)

Data 7

Data 6

Data 5

Data 4

Data 3

Data 2

Data 1

Data 0

DRR (W)

Data Rate

Bit 1

Bit 0

DKR (R)

DSKCHG

Inverse

ST0

Interrupt

Seek

Head

DRV 1

DRV 0

Code

End

Track 0

Addr

(Exec)

ST1

End

CRC

Data

WRT

Missing

Error

Overrun

Data

PRT

Address

Track

Mark

ST2

CRC

Scan

Missing

Control

Error in

Wrong

Equal

Not

Bad

Address

Mark

Data Fld

Track

Hit

Satisfied

Track

Mark in

Data Fld

ST3

Write

Track 0

Head

DRV 1

DRV 0

Protect

Status

Select

(Exec)

Status

X e Don’t Care

Z e TRI-STATE

Processor Software Interface

Bytes are transferred to and from the disk controller in dif-

ferent ways for the different phases in a command

COMMAND SEQUENCE

The disk controller can perform various disk transfer and

head movement commands Most commands involve three

separate phases

Command Phase

The mP writes a series of bytes to the

Data Register These bytes indicate the command desired

and the particular parameters required for the command All

the bytes must be written in the order specified in the Com-

mand Description Table The Execution Phase starts imme-

diately after the last byte in the Command Phase is written

Prior to performing the Command Phase the Drive Control

and Data Rate Registers should be set

Execution Phase

The disk controller performs the desired

command Some commands require the mP to read or write

data to or from the Data Register during this time Reading

data from a disk is an example of this

Result Phase

The mP reads a series of bytes from the data

cuted properly and other pertinent information The bytes

are read in the order specified in the Command Description

Table

A new command may be initiated by writing the Command

Phase bytes after the last bytes required from the Result

Phase have been read If the next command requires se-

lecting a different drive or changing the data rate the Drive

Control and Data Rate Registers should be updated If the

command is the last command then the software should

deselect the drive

(Note as a general rule the operation of

the controller core is independent of how the mP updates

the Drive Control and Data Rate Registers The software

must ensure that manipulation of these registers is coordi-

nated with the controller operation)

During the Command Phase and the Result Phase bytes

are transferred to and from the Data Register The Main

Status Register is monitored by the software to determine

when a data transfer can take place Bit 6 of the Main

Status Register must be clear and bit 7 must be set before a

byte can be written to the Data Register during the Com-

mand Phase Bits 6 and 7 of the Main Status Register must

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