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HT45F65 Datasheet(PDF) 160 Page - Holtek Semiconductor Inc

Part # HT45F65
Description  Glucose Meter 8-Bit Flash MCU
PDF  231 Pages
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Manufacturer  HOLTEK [Holtek Semiconductor Inc]
Direct Link  http://www.holtek.com
Logo HOLTEK - Holtek Semiconductor Inc

HT45F65 Datasheet(HTML) 160 Page - Holtek Semiconductor Inc

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HT45F65/HT45F66/HT45F67
Glucose Meter 8-Bit Flash MCU
I2C Interface
TheI2Cinterfaceisusedtocommunicatewithexternalperipheraldevicessuchassensorsetc.
OriginallydevelopedbyPhilips,itisatwolinelowspeedserialinterfaceforsynchronousserial
datatransfer.Theadvantageofonlytwolinesforcommunication,relativelysimplecommunication
protocolandtheabilitytoaccommodatemultipledevicesonthesamebushasmadeitanextremely
popularinterfacetypeformanyapplications.
De vi ce
Sl av e
De vi ce
Ma st er
De vi ce
Sl av e
VD D
SD A
SC L
I2C Master/Slave Bus Connection
I2C Interface Operation
TheI2Cserialinterfaceisatwolineinterface,aserialdataline,SDA,andserialclockline,SCL.As
manydevicesmaybeconnectedtogetheronthesamebus,theiroutputsarebothopendraintypes.
Forthisreasonitisnecessarythatexternalpull-highresistorsareconnectedtotheseoutputs.Note
thatnochipselectlineexists,aseachdeviceontheI2Cbusisidentifiedbyauniqueaddresswhich
willbetransmittedandreceivedontheI2Cbus.
WhentwodevicescommunicatewitheachotheronthebidirectionalI2Cbus,oneisknownasthe
masterdeviceandoneastheslavedevice.Bothmasterandslavecantransmitandreceivedata,
however,itisthemasterdevicethathasoverallcontrolofthebus.Forthisdevice,whichonly
operatesinslavemode,therearetwomethodsoftransferringdataontheI2Cbus,theslavetransmit
modeandtheslavereceivemode.
ThereareseveralconfigurationoptionsassociatedwiththeI2Cinterface.Oneoftheseistoenable
thefunctionwhichselectstheSIMpinsratherthannormalI/Opins.Notethatiftheconfiguration
optiondoesnotselecttheSIMfunctionthentheSIMENbitintheSIMC0registerwillhaveno
effect.AconfigurationoptionexiststoallowaclockotherthanthesystemclocktodrivetheI2C
interface.AnotherconfigurationoptiondeterminesthedebouncetimeoftheI2Cinterface.Thisuses
theinternalclocktoineffectaddadebouncetimetotheexternalclocktoreducethepossibilityof
glitchesontheclocklinecausingerroneousoperation.Thedebouncetime,ifselected,canbechosen
tobeeither1or2systemclocks.
ST AR T si gnal
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S end sl av e a ddr es s
and R/ W bi t f ro m Ma st er
Ac kn ow le dge
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Se nd d at a by te
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ST OP s i gnal
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