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HT45F75 Datasheet(PDF) 126 Page - Holtek Semiconductor Inc |
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HT45F75 Datasheet(HTML) 126 Page - Holtek Semiconductor Inc |
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126 / 190 page ![]() Rev. 1.10 1�� De�e��e� 1�� �01� Rev. 1.10 1�7 De�e��e� 1�� �01� HT45F75 Body Fat Scale Flash MCU HT45F75 Body Fat Scale Flash MCU I2C Bus Slave Address Acknowledge Signal Afterthemasterhastransmittedacallingaddress,anyslavedeviceontheI2Cbus,whose owninternaladdressmatchesthecallingaddress,mustgenerateanacknowledgesignal.The acknowledgesignalwillinformthemasterthataslavedevicehasaccepteditscallingaddress.Ifno acknowledgesignalisreceivedbythemasterthenaSTOPsignalmustbetransmittedbythemaster toendthecommunication.WhentheHAASflagishigh,theaddresseshavematchedandtheslave devicemustchecktheSRWflagtodetermineifitistobeatransmitterorareceiver.IftheSRWflag ishigh,theslavedeviceshouldbesetuptobeatransmittersotheHTXbitintheSIMC1register shouldbesethigh.IftheSRWflagislow,thenthemicrocontrollerslavedeviceshouldbesetupasa receiverandtheHTXbitintheSIMC1registershouldbeclearedtozero. I2C Bus Data and Acknowledge Signal Thetransmitteddatais8-bitswideandistransmittedaftertheslavedevicehasacknowledged receiptofitsslaveaddress.TheorderofserialbittransmissionistheMSBfirstandtheLSBlast. Afterreceiptof8-bitsofdata,thereceivermusttransmitanacknowledgesignal,level“0”,before itcanreceivethenextdatabyte.Iftheslavetransmitterdoesnotreceiveanacknowledgebitsignal fromthemasterreceiver,thentheslavetransmitterwillreleasetheSDAlinetoallowthemaster tosendaSTOPsignaltoreleasetheI2CBus.ThecorrespondingdatawillbestoredintheSIMD register.Ifsetupasatransmitter,theslavedevicemustfirstwritethedatatobetransmittedintothe SIMDregister.Ifsetupasareceiver,theslavedevicemustreadthetransmitteddatafromtheSIMD register. Whentheslavereceiverreceivesthedatabyte,itmustgenerateanacknowledgebit,knownas TXAK,onthe9thclock.Theslavedevice,whichissetupasatransmitterwillchecktheRXAKbit intheSIMC1registertodetermineifitistosendanotherdatabyte,ifnotthenitwillreleasethe SDAlineandawaitthereceiptofaSTOPsignalfromthemaster. Da ta 10 1 00 1 0 0 1 0 01010 1 1 S= St ar t ( 1 bi t) SA =S la ve A dd re ss ( 7 bi ts ) SR =S RW b it ( 1 bi t) M= Sl av e de vi ce s end a ckn ow le dge bi t (1 b it ) D= Da ta ( 8 bi ts ) A= AC K ( RX AK b it f or tr an sm i tte r, T XAK b it fo r re ce iv er 1 b it ) P= St op ( 1 bi t) SC L St ar t SD A SR W AC K AC K St op SC L SD A Sl av e Ad dr es s SS AS R MD AD A SS AS R MD AD AP I2C Communication Timing Diagram Note:*Whenaslaveaddressismatched,thedevicemustbeplacedineitherthetransmitmode andthenwritedatatotheSIMDregister,orinthereceivemodewhereitmustimplementa dummyreadfromtheSIMDregistertoreleasetheSCLline. |
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