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HT45F75 Datasheet(PDF) 130 Page - Holtek Semiconductor Inc |
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HT45F75 Datasheet(HTML) 130 Page - Holtek Semiconductor Inc |
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130 / 190 page  Rev. 1.10 130 De�e��e� 1�� �01� Rev. 1.10 131 De�e��e� 1�� �01� HT45F75 Body Fat Scale Flash MCU HT45F75 Body Fat Scale Flash MCU DatatobereceivedbytheUARTisacceptedontheexternalRXpin,fromwhereitisshiftedin, LSBfirst,totheReceiverShiftRegisterataratecontrolledbytheBaudRateGenerator.When theshiftregisterisfull,thedatawillthenbetransferredfromtheshiftregistertotheinternalRXR register,whereitisbufferedandcanbemanipulatedbytheapplicationprogram.OnlytheRXR registerismappedontotheMCUDataMemory,theReceiverShiftRegisterisnotmappedandis thereforeinaccessibletotheapplicationprogram. Itshouldbenotedthattheactualregisterfordatatransmissionandreception,althoughreferredto inthetext,andinapplicationprograms,asseparateTXRandRXRregisters,onlyexistsasasingle sharedregisterintheDataMemory.ThissharedregisterknownastheTXRRXRregisterisusedfor bothdatatransmissionanddatareception. MSB LSB ………………………… T�ans�itte� Shift Registe� (TSR) MSB LSB ………………………… Re�eive� Shift Registe� (RSR) TX Pin RX Pin Baud Rate Gene�ato� TX Registe� (TXR) RX Registe� (RXR) Data to �e t�ans�itted Data �e�eived Buffe� fSYS MCU Data Bus UART Data Transfer Scheme UART Status and Control Registers TherearefivecontrolregistersassociatedwiththeUARTfunction.TheUSR,UCR1andUCR2 registerscontroltheoverallfunctionoftheUART,whiletheBRGregistercontrolstheBaud rate.Theactualdatatobetransmittedandreceivedontheserialinterfaceismanagedthroughthe TXRRXRdataregister. Register Name Bit 7 6 5 4 3 2 1 0 USR PERR NF FERR OERR RIDLE RXIF TIDLE TXIF UCR1 UARTEN BNO PREN PRT STOPS TXBRK RX8 TX8 UCR� TXEN RXEN BRGH ADDEN WAKE RIE TIIE TEIE TXRRXR TXRXD7 TXRXD� TXRXD5 TXRXD� TXRXD3 TXRXD� TXRXD1 TXRXD0 BRG BRGD7 BRGD� BRGD5 BRGD� BRGD3 BRGD� BRGD1 BRGD0 UART Register Summary USR Register TheUSRregisteristhestatusregisterfortheUART,whichcanbereadbytheprogramtodetermine thepresentstatusoftheUART.AllflagswithintheUSRregisterarereadonly.Furtherexplanation oneachoftheflagsisgivenbelow: Bit 7 6 5 4 3 2 1 0 Na�e PERR NF FERR OERR RIDLE RXIF TIDLE TXIF R/W R R R R R R R R POR 0 0 0 0 1 0 1 1 Bit7 PERR:Parityerrorflag 0:Noparityerrorisdetected 1:Parityerrorisdetected |
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